Semiconductor integrated circuit device

• US 20100308458A1
• Filed: 07/21/2010
• Published: 12/09/2010
• Est. Priority Date: 12/18/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Shinozaki, Masao, Akioka, Takashi, Asari, Sanae, Kohara, Yutaka, Miyata, Shusaku, Nishimoto, Kenji, Nakazato, Shinji
• Granted Patent: US 7,982,314 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Claims

1. A semiconductor integrated circuit device comprising:

circuit elements and wirings which are provided on a main surface of a semiconductor substrate and constitute a semiconductor integrated circuit;

a first insulating film (150) provided over the circuit elements and the wirings (FIGS. 17,18, on line 10 of page 22-line 16 of page

     24);

a first pad electrode (04, Metal PAD) and a second pad electrode (04, Metal PAD) provided over the first insulating film (150) (FIGS. 1-7);

a protective film (203) provided over the circuit except for openings over surfaces of the first and second pad electrodes (FIGS. 15,17,18,19, on line 10 of page 22-line 19 of page

     27);

a second insulating film (02,204) provided over the protective film (203) except for the openings (FIGS. 15,19); and

a first conductive layer (05,105,205,305,405,505, WPP WIRING LAYER), for electrically connecting to a first external terminal (03, WPP BUMP), provided over the second insulating film (204) and electrically connected to the first pad electrode and the second pad electrode (FIGS. 1-7).

2. The semiconductor integrated circuit device according to claim 1, further comprising:

a second conductive layer (605), for electrically connecting to a second external terminal (03, WPP BUMP), provided over the second insulating film (204) and electrically connected to a third pad electrode (FIG. 2),

wherein a width of the first conductive layer is greater than a width of the second conductive layer (on lines 5-22 of page

     7).

3. The semiconductor integrated circuit device according to claim 2,

wherein the first conductive layer serves for electrically connecting to a third external terminal (03, WPP BUMP) different from the first external terminal (FIGS. 1-2).

4. The semiconductor integrated circuit device according to claim 1,

wherein the first conductive layer serves for electrically connecting to a second external terminal (03, WPP BUMP) different from the first external terminal (FIGS. 1-2).

5. The semiconductor integrated circuit device according to claim 1, wherein a width of the first conductive layer is greater than a width of the first external terminal (FIG. 1).

6. The semiconductor integrated circuit device according to claim 1, wherein first external terminal (03, WPP BUMP) is a bump electrode.

7. The semiconductor integrated circuit device according to claim 1, wherein the first pad electrode and the second pad electrode are respectively bonding pads.

8. The semiconductor integrated circuit device according to claim 1, wherein the protective film (203) includes a silicon nitride film, wherein the second insulating film (02,204) includes a polyimide film.

17. The semiconductor integrated circuit device according to claim 1, wherein a thickness of the first conductive layer being greater than a thickness of the first pad electrode and the second pad electrode (on lines 10-11 of page 23, on lines 21-25 of page 25).

9. A semiconductor integrated circuit device comprising:

circuit elements and wirings which are provided on a main surface of a semiconductor substrate and constitute a semiconductor integrated circuit;

a first insulating film (150) provided over the circuit elements and the wirings (FIGS. 17,18, on line 10 of page 22-line 16 of page

     24);

a first pad electrode (04, Metal PAD) provided over the first insulating film (150) (FIGS. 1-9);

a protective film (203) provided over the circuit except for an opening over a surface of the first pad electrode (FIGS. 15,17,18,19, on line 10 of page 22-line 19 of page

     27);

a second insulating film (02,204) provided over the protective film (203) except for the opening (FIGS. 15,19); and

a first conductive layer (05,105,205,305,405,505, WPP WIRING LAYER), for electrically connecting to a first external terminal (03, WPP BUMP) and a second external terminal (03, WPP BUMP), provided over the second insulating film (204) and electrically connected to the first pad electrode and the second pad electrode (FIG. 5 as well as FIGS. 8,10,1-7).

10. The semiconductor integrated circuit device according to claim 9, further comprising:

a second conductive layer (605), for electrically connecting to a third external terminal (WPP BUMP), provided over the second insulating film (204) and electrically connected to a second pad electrode (FIG. 2),

wherein a width of the first conductive layer is greater than a width of the second conductive layer (on lines 5-22 of page

     7).

11. The semiconductor integrated circuit device according to claim 10, further comprising:

a third pad electrode (04, Metal PAD) provided over the first insulating film (150) (FIGS. 1-9),

the protective film (203) provided over the circuit except for an opening over a surface of the third pad electrodes (FIGS. 15,17,18,19, on line 10 of page 22-line 19 of page

     27),

the second insulating film (02,204) provided over the protective film (203) except for the opening (FIGS. 15,19),

the first conductive layer (05,105,205,305,405,505, WPP WIRING LAYER) serves for electrically connecting to the third external terminal (03, WPP BUMP) different from the first external terminal (FIGS. 1-2).

12. The semiconductor integrated circuit device according to claim 9, further comprising:

a second pad electrode (04, Metal PAD) provided over the first insulating film (150) (FIGS. 1-9),

the protective film (203) provided over the circuit except for an opening over a surface of the second pad electrodes (FIGS. 15,17,18,19, on line 10 of page 22-line 19 of page

     27),

the second insulating film (02,204) provided over the protective film (203) except for the opening (FIGS. 15,19),

the first conductive layer (05,105,205,305,405,505, WPP WIRING LAYER) serves for electrically connecting to the second external terminal (03, WPP BUMP) different from the first external terminal (FIGS. 1-2).

13. The semiconductor integrated circuit device according to claim 9, wherein first external terminal (03, WPP BUMP) is a bump electrode.

14. The semiconductor integrated circuit device according to claim 9, wherein the first pad electrode and the second pad electrode are respectively bonding pads.

15. The semiconductor integrated circuit device according to claim 9, wherein the protective film (203) includes a silicon nitride film, wherein the second insulating film (02,204) includes a polyimide film.

16. The semiconductor integrated circuit device according to claim 9, wherein a width of the first conductive layer is greater than a width of the first external terminal (03, WPP BUMP) and the second external terminal (FIG. 1).

18. The semiconductor integrated circuit device according to claim 9, wherein a thickness of the first conductive layer being greater than a thickness of the first pad electrode and the second pad electrode (on lines 10-11 of page 23, on lines 21-25 of page 25).