SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

• US 20100308468A1
• Filed: 03/02/2009
• Published: 12/09/2010
• Est. Priority Date: 03/14/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Fukuda, Toshiyuki, Itooka, Toshimasa, Utatsu, Hiroki, Furuyashiki, Junya, Yoshikawa, Noriyuki
• Application Number:
  US12/867,804
• Publication Number:
  US 20100308468A1
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In a semiconductor device made of a plurality of materials, if the device is fabricated through a step of cutting the bonded plurality of materials, a boundary line of the plurality of materials is exposed on a cutting plane. Internal stress in the cutting remains at this boundary line to allow moisture and corrosive gas to easily enter into the device. In order to reduce the entrance of the moisture, the gas, and the like, the boundary appearing on the cutting plane is covered by a covering layer. At this time, partial cutting exposing the boundary line and not separating semiconductor devices are performed so that the covering layer can be formed with the plurality of semiconductor devices attached to the substrate.

Claims

1. A semiconductor device comprising:

a base including at least one external terminal and an element mounting portion;

a semiconductor element mounted on the element mounting portion;

a connecting portion electrically connecting the external terminal and the semiconductor element; and

first resin covering the semiconductor element and the connecting portion, wherein

at least part of a boundary line being an end of a boundary plane between the base and the first resin is covered with a covering layer, the part existing on at least one cutting plane along which the base and the first resin are cut.

2. The semiconductor device of claim 1, wherein

a part of the cutting plane formed by the base includes a part projecting more outward than a part of the cutting plane formed by the first resin exists.

3. The semiconductor device of claim 1 or 2, wherein

the base is a substrate including the element mounting portion and the external terminal.

4. The semiconductor device of claim 1 or 2, wherein

the first resin covers a part of a surface of the substrate, on which the semiconductor element is mounted.

5. The semiconductor device of claims 1 or 2, wherein

the connecting portion is a metal thin wire or a projecting bump.

6. The semiconductor device of claims 1 or 2, wherein

the substrate is a rectangle plate,

multiple ones of the at least one external terminal are arranged on two facing sides of the substrate, and

multiple ones of the at least one cutting plane are two facing sides of the substrate, which are not provided with the external terminals.

7. The semiconductor device of claims 1 or 2, wherein

the cutting plane includes a curbed surface.

8. The semiconductor device of claims 1 or 2, wherein

the covering layer completely covers the boundary line between the first resin and the substrate.

9. The semiconductor device of claim 1 or 2, wherein

the element mounting portion is a die pad, and

the boundary line on the cutting plane is a boundary line between the external terminal and the first resin.

10. The semiconductor device of claim 9, wherein

the external terminal includes a portion supported by second resin, and

the cutting plane further includes a second resin boundary line being an end of a boundary plane between the external terminal and the second resin.

11. The semiconductor device of any one of claims 1 or 2, wherein

the first resin is translucent, and

the covering layer has a transmittance of 85% or more.

12. The semiconductor device of any one of claims 1 or 2, wherein

the covering layer has a refractive index of 1.8 or less.

13. A fabrication method of a semiconductor device comprising:

mounting a semiconductor element on a substrate body including at least one through hole and provided with an external terminal in the through hole;

electrically connecting the semiconductor element to a part of the external terminal;

encapsulating the semiconductor element and the part of the external terminal with resin;

newly exposing a boundary line being an end of a boundary plane between the substrate body and the resin by cutting the resin and a part of the substrate body in a thickness direction;

forming a covering layer covering the boundary line; and

cutting a residual which has not been cut in the exposing and remains in the thickness direction of the substrate body to separate the substrate body into individual substrates.

14. The method of claim 13, wherein

at least one through hole is a slit, and is a plurality of through holes formed parallel to each other in the substrate body, and

the boundary line is substantially vertical to a direction in which the slit extends.

15. The method of claim 13, wherein

the exposing is cutting with a blade having a U-shaped cross-section.

16. The method of claim 13, wherein

the exposing is cutting with a blade having a taper on a side surface.

17. A fabrication method of a semiconductor device comprising:

mounting a semiconductor element on a die pad of a base which is a lead frame including the die pad and an external terminal;

electrically connecting the semiconductor element to the external terminal;

encapsulating the semiconductor element and the external terminal with first resin;

exposing a boundary line being an end of a boundary plane between the external terminal and the first resin by cutting the first resin and a part of the external terminal in a thickness direction;

forming a covering layer covering the boundary line; and

cutting a residual which has not been cut in the exposing and remains in the thickness direction of the external terminal.

18. The method of claim 17, wherein

the external terminal includes a part having a double layer structure of a metal layer and a second resin layer of second resin, and

the exposuring is exposure of a boundary line being an end of a boundary plane between the metal layer and the first resin, and a second resin boundary line being an end of a boundary plane between the metal layer and the second resin layer by cutting the first resin, the metal layer, and a part of the second resin layer.