Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone
First Claim
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1. An application-specific integrated semiconductor circuit (ASIC), comprising:
- an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and
an array of wiring zones corresponding to the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones disposed in at least two wiring layers comprising wiring lines, wherein the wiring lines in the at least two wiring layers are not parallel to one another, wherein the wiring lines in at least one of the two wiring layers comprise line segments that are continuous within a wiring zone of the array of wiring zones, and wherein the line segments are interrupted at wiring zone boundaries.
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Abstract
An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
192 Citations
25 Claims
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1. An application-specific integrated semiconductor circuit (ASIC), comprising:
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an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and an array of wiring zones corresponding to the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones disposed in at least two wiring layers comprising wiring lines, wherein the wiring lines in the at least two wiring layers are not parallel to one another, wherein the wiring lines in at least one of the two wiring layers comprise line segments that are continuous within a wiring zone of the array of wiring zones, and wherein the line segments are interrupted at wiring zone boundaries. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An application-specific integrated semiconductor circuit (ASIC), comprising:
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an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and an array of wiring zones corresponding to the array of logic function blocks and disposed over the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones comprising first line segments in the first wiring layer and second line segments disposed over the first line segments in a second wiring layer, the first and the second line segments being continuous within a wiring zone of the array of wiring zones, wherein the first and the second line segments are interrupted at boundaries between wiring zones of the array of wiring zones. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. An application-specific integrated semiconductor circuit (ASIC), comprising:
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an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and an array of wiring zones corresponding to the array of logic function blocks and disposed over the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones comprising first line segments in the first wiring layer and second line segments disposed over the first line segments in a second wiring layer, the first and the second line segments being continuous within a wiring zone of the array of wiring zones, wherein the first and the second line segments are interrupted at boundaries between wiring zones of the array of wiring zones, wherein, at a first wiring zone boundary, the first line segments of a wiring zone of the array of wiring zones are coupled to the corresponding first line segments of an adjacent wiring zone of the array of wiring zones through first mask programmable switches, wherein, at a second wiring zone boundary, the second line segments of a wiring zone of the array of wiring zones are coupled to the corresponding second line segments of an adjacent wiring zone of the array of wiring zones through second mask programmable switches, wherein each line of the first line segments is coupled to a corresponding line of the second line segments through a third mask programmable switch. - View Dependent Claims (23, 24, 25)
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Specification