ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY

• US 20100309211A1
• Filed: 08/16/2010
• Published: 12/09/2010
• Est. Priority Date: 08/26/1996
• Status: Active Grant

• Current Assignee: Parthenon Unified Memory Architecture LLC (Acacia Research Corporation)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Diaz, Raul Zegers, Colavin, Osvaldo, Owen, Jefferson Eugene
• Granted Patent: US 7,898,548 B2
• Time in Patent Office: Days
• US Class Current: 345/541
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Claims

1. A computing system comprising:

a memory configured to store compressed image data in a compressed data buffer structure, the memory further configured to store intra-picture image data in a first image buffer and predicted-picture image data in a second image buffer;

a memory interface coupled to the memory and configured to arbitrate access to the memory;

a central processing unit (CPU) coupled to the memory interface and configured to direct operations of the computing system, the CPU sharing the memory with peripheral devices in the computing system;

a video controller configured to decode bidirectional image data and send the decoded bidirectional image data to a display adapter;

an encoder/decoder configured to share the memory, the encoder/decoder further configured retrieve compressed image data from the compressed data buffer structure and send intra-picture image data to the first image buffer and predicted-picture image data to the second image buffer;

the encoder/decoder further configured to send bidirectional image data to the video controller; and

a bus coupled to the memory interface, the encoder/decoder, and the video controller, the bus having sufficient capacity to operate as the only bus in the computing system configured to transfer data in real time between the memory, the encoder/decoder, and the video controller.

2. The computing system of claim 1, wherein the memory includes a DRAM.

3. The computing system of claim 1, wherein the memory interface is configured to arbitrate access requests from the CPU, the decoder/encoder, and the video controller.

4. The computing system of claim 1, wherein the CPU further includes a cache memory configured to store non-image data.

5. The computing system of claim 1, further comprising:

a source of compressed image data coupled to the bus, the source configured to stream the compressed image data to the memory according to a fast bus protocol.

6. The computing system of claim 1, wherein the video controller is configured to send decoded image data to the display adapter according to an RGB protocol.

7. The computing system of claim 1, wherein the bus operates according to a peripheral component interconnect (PCI) bus protocol.

8. The computing system of claim 1, wherein the bus operates according to an accelerated graphics port (AGP) bus protocol.

9. The computing system of claim 1, wherein the bus operates according to a non-standardized bus protocol.

10. The computing system of claim 1, wherein the compressed data buffer structure of the memory configurable dynamically.