Cable Modem System with Sample and Packet Synchronization

• US 20100309935A1
• Filed: 08/16/2010
• Published: 12/09/2010
• Est. Priority Date: 02/12/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Horton, John D. JR., Rabenko, Theodore F., Thi, James C.H.
• Granted Patent: US 8,718,091 B2
• Time in Patent Office: Days
• US Class Current: 370/509
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A method and system of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable modem over a cable modem termination system, to a voice packet recipient. Unsolicited grant arrivals in response to a request from the voice packet sender coupled to the cable modem are determined. The storing of sampled voice packets is synchronized with the unsolicited grant arrivals. Upon receipt of an unsolicited grant arrival, currently stored sampled voice packets are transmitted to the cable modem for further transmission to the voice packet recipient over the cable modem termination system.

Claims

1. An apparatus for synchronizing a first clock signal to a second clock signal, comprising:

a downstream receiver configured to receive a downstream information flow, the downstream information flow including a timestamp message and a slot timing error message, the timestamp message indicating a frequency of the first clock signal and the slot timing error indicating a difference between the first frequency of the first clock signal and a frequency of a second clock signal;

a timebase message detector configured to provide an absolute timing reference based upon the timestamp message;

a tracking loop configured to provide a local time reference based upon the absolute timing reference; and

a first summer configured to provide the second clock signal based upon a combination of the local time reference and the slot timing error message.

2. The apparatus of claim 1, wherein the absolute timing reference represents the frequency of the first clock signal.

3. The apparatus of claim 1, wherein the local time reference corresponds closely in frequency to the frequency of the first clock signal.

4. The apparatus of claim 1, wherein the tracking loop comprises:

a differencing circuit configured to determine a difference between the absolute timing reference and the local time reference;

a numerically controlled oscillator configured to provide an oscillator drive signal based upon the difference; and

a local time reference generator configured to provide the local time reference based upon the oscillator drive signal.

5. The apparatus of claim 4, wherein the local time reference generator is configured to be driven in a manner which closely matches the frequency of the frequency of the first clock signal.

6. The apparatus of claim 1, wherein the tracking loop further comprises:

a loop filter configured to filter the frequency error value to provide a filtered error value,

wherein the numerically controlled oscillator is further configured to provide the oscillator drive signal based upon the filtered error value.

7. The apparatus of claim 1, further comprising:

a second summer configured to combine the local time reference and an initial slot timing offset to provide a partially slot timing offset corrected output,

wherein the first summer is further configured to combine the partially slot timing offset corrected output and the local time reference to provide the second clock signal.

8. The apparatus of claim 7, wherein the initial slot timing offset represents an approximation of an expected slot timing offset likely to occur.

9. The apparatus of claim 7, wherein the initial slot timing offset represents the approximation of the expected slot timing offset likely to occur due to propagation and processing delays.

10. The apparatus of claim 1, further comprising:

a scaler configured to scale the second clock signal to provide a time scaled reference.

11. The apparatus of claim 9, further comprising:

a third summer configured to compare the time scaled reference to a designated transmit time, the third summer being configured to cause an initiate burst command to be issued when the designated transmit time is equal to the time scaled reference.

12. The apparatus of claim 10, further comprising:

an upstream data queue configured to store data for transmission over a communication channel; and

a modulator configured to transmit the data over the communication channel in response to the initiate burst command being issued.

13. A method for synchronizing a first clock signal to a second clock signal, comprising:

(a) receiving a downstream information flow, the downstream information flow including a timestamp message and a slot timing error message, the timestamp message indicating a frequency of the first clock signal and the slot timing error indicating a difference between the first frequency of the first clock signal and a frequency of a second clock signal;

(b) providing an absolute timing reference based upon the timestamp message;

(c) providing a local time reference based upon the absolute timing reference; and

(d) combining the providing the second clock signal based upon a combination of the local time reference and the slot timing error message.

14. The method of claim 13, wherein the absolute timing reference represents the frequency of the first clock signal.

15. The method of claim 13, wherein the local time reference corresponds closely in frequency to the frequency of the first clock signal.

16. The method of claim 13, wherein step (c) comprises:

(c)(i) determining a difference between the absolute timing reference and the local time reference;

(c)(ii) providing an oscillator drive signal based upon the difference; and

(c)(iii) providing the local time reference based upon the oscillator drive signal.

17. The method of claim 13, wherein step (c) further comprises:

(c)(iv) filtering the frequency error value to provide a filtered error value, and

wherein step (c)(ii) comprises;

(c)(ii)(A) providing the oscillator drive signal based upon the filtered error value.

18. The method of claim 13, further comprising:

(e) combining the local time reference and an initial slot timing offset to provide a partially slot timing offset corrected output, and

wherein step (d) comprises;

(d)(i) combining the partially slot timing offset corrected output and the local time reference to provide the second clock signal.

19. The method of claim 18, wherein the initial slot timing offset represents an approximation of an expected slot timing offset likely to occur.

20. The method of claim 18, wherein the initial slot timing offset represents the approximation of the expected slot timing offset likely to occur due to propagation and processing delays.

21. The method of claim 13, further comprising:

(e) scaling the second clock signal to provide a time scaled reference.

22. The method of claim 21, further comprising:

(f) comparing the time scaled reference to a designated transmit time; and

(g) causing an initiate burst command to be issued when the designated transmit time is equal to the time scaled reference.

23. The method of claim 22, further comprising:

(h) storing data for transmission over a communication channel; and

(i) transmitting the data over the communication channel in response to the initiate burst command being issued.