Methods and systems for DSP-based receivers

• US 20100310024A1
• Filed: 08/16/2010
• Published: 12/09/2010
• Est. Priority Date: 07/21/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gopinathan, Venugopal, Agazzi, Oscar
• Granted Patent: US 8,363,683 B2
• Time in Patent Office: Days
• US Class Current: 375/346
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/0609 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/697 Arrangements for reducing noise and distortion
• CPC Class Codes: H04B 10/6971 using equalisation
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03133 with a non-recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03203 Trellis search techniques
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Claims

1. (canceled)

2. A method, comprising:

(a) receiving a data signal;

(b) generating N sampling signals, each of said N sampling signals having a respective phase;

(c) sampling said data signal with said N sampling signals to generate N samples;

(d) individually adjusting each of said N sampling signals to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples; and

(e) generating a digital signal representative of said received data signal from said N samples.

3. The method of claim 2, wherein each of said N samples have a sampling rate lower than a symbol rate of said data signal.

4. The method of claim 2, wherein said N sampling signals are time-staggered relative to each other.

5. The method of claim 2, wherein said sampling phase errors are caused by periodic jitter in said N sampling signals.

6. The method of claim 2, wherein step (b) comprises sampling said data signal with said N sampling signals in respective analog-to-digital converter (ADC) paths.

7. The method of claim 6, wherein said gain errors are caused by gain mismatches among said ADC paths.

8. The method of claim 2, wherein said offsets cause offset mismatches among said N samples.

9. The method of claim 2, wherein step (d) further comprises measuring said offsets in a digital domain and individually adjusting for said offsets in said digital domain for each of said N sampling signals.

10. The method of claim 9, wherein step (d) further comprises measuring said offsets in an M-path parallel decision feedback equalizer (DFE) and individually adjusting one or more DFE DC taps associated with each of said N sampling signals.

11. The method of claim 2, wherein step (d) further comprises measuring said offsets in a digital domain and individually adjusting for said offsets in an analog domain for each of said N sampling signals.

12. The method of claim 11, wherein step (d) further comprises measuring said offsets in an M-path parallel decision feedback equalizer (DFE) and individually adjusting reference voltages of respective analog-to-digital converters associated with each of said N sampling signals.

13. The method of claim 2, wherein step (d) further comprises measuring said gain errors in a digital domain and individually adjusting for said gain errors in said digital domain for each of said N sampling signals.

14. The method of claim 2, wherein step (d) further comprises measuring said gain errors in an M-path parallel feed-forward equalizer (FFE) and individually adjusting one or more FFE taps associated with each of said N sampling signals.

15. The method of claim 2, wherein step (d) further comprises measuring said gain errors in a digital domain and individually adjusting for said gain errors in an analog domain for each of said N sampling signals.

16. The method of claim 2, wherein step (d) further comprises measuring said sampling phase errors in respective phase detectors and individually adjusting for said sampling phase errors in a timing recovery module for each of said N sampling signals.

17. A receiver, comprising:

a timing recovery module that generates N sampling signals having time-staggered phases;

an analog-to-digital converter (ADC) array of N ADC paths that receives a data signal and that samples said data signal according to said N sampling signals to generate N samples; and

a compensation module configured to individually adjust each of said N ADC paths to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples.

18. The receiver of claim 17, wherein said compensation module comprises N timing recovery loops, each of said N timing recovery loops coupled to a respective one of said N ADC paths and configured to adjust for a respective sampling phase error in said respective one of said N ADC paths.

19. The receiver of claim 17, wherein said compensation module comprises an M-path parallel decision feedback equalizer (DFE) having configurable DFE DC taps to adjust for said offsets in said N samples.

20. The receiver of claim 17, wherein said compensation module comprises a programmable gain amplifier (PGA) array of N PGAs, each of said PGAs coupled to a respective one of said N ADC paths and configured to adjust for a respective gain error in said respective one of said N ADC paths.

21. The receiver of claim 17, wherein each of said N samples have a sampling rate lower than a symbol rate of said data signal.