DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY

• US 20100310995A1
• Filed: 02/09/2010
• Published: 12/09/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chun-Kuang, Hsu, Feng-Cheng, Lin, Chih-An, Wang, Chien-Wei, Yeh, Hsiao-Wei
• Granted Patent: US 8,741,552 B2
• Time in Patent Office: Days
• US Class Current: 430/326
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: G03F 7/38 Treatment before imagewise removal, e.g. prebaking G03F7/265 takes precedence
• CPC Class Codes: G03F 7/40 Treatment after imagewise removal, e.g. baking
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern.

Claims

1. A lithography patterning method comprising:

forming a first resist pattern on a substrate, the first resist pattern having a plurality of openings therein on the substrate;

baking the first positive resist pattern to form a baked resist pattern; and

forming a second resist layer on the substrate and within the plurality of openings of the baked resist pattern, wherein the baked resist pattern is insoluble in the second positive resist layer.

2. The method of claim 1, wherein the first resist pattern is formed by a first positive resist layer having thermal-acid generator, cross-linker, surfactant or high-dissolution agent therein.

3. The method of claim 1, wherein the second resist layer is a second positive resist layer.

4. The method of claim 1, further comprising:

exposing the second resist layer, defining at least one opening in the second resist layer; and

applying a chemical to remove the baked resist.

5. The method of claim 1, further comprising:

exposing the second resist layer, defining a plurality of exposed and unexposed features on the substrate; and

applying a chemical to remove the baked resist pattern and the exposed features, leaving the unexposed features on the substrate.

6. The method of claim 1, further comprising:

exposing the second resist layer, defining a plurality of exposed and unexposed features on the substrate; and

applying a developer solvent to remove the exposed features, leaving the unexposed features on the substrate; and

applying an etching process to selectively remove the baked resist pattern relative to the unexposed features.

7. The method of claim 5, wherein the chemical is a developer solvent.

8. A lithography patterning method comprising:

forming a first resist pattern on a substrate, the first resist pattern having a plurality of openings therein on the substrate;

baking the first resist pattern to form a baked resist pattern;

forming a second resist layer on the substrate and within the plurality of openings of the baked resist pattern;

exposing the second resist layer to form at least one exposed feature and at least one unexposed feature on the substrate; and

forming a second resist pattern by removing the baked resist pattern and the exposed feature, leaving the unexposed feature intact.

9. The method of claim 8, wherein the first resist pattern is formed by a first positive resist layer having thermal-acid generator, cross-linker, or high-dissolution agent therein.

10. The method of claim 8, wherein the baked resist pattern is insoluble in the second resist layer.

11. The method of claim 8, wherein the baked resist pattern and the exposed feature are removed by a developer solvent.

12. The method of claim 8, wherein baked resist pattern is soluble in the developer solvent.

13. The method of claim 8, wherein the first resist pattern is baked to a temperature about 100°

C. to about 250°

C. for about 20 sec to about 200 sec

14. A method of double patterning, comprising:

forming a first positive resist pattern on a substrate, the first positive resist pattern is formed by a first positive resist layer having a plurality of openings therein, and the first positive resist layer comprises thermal-acid generator, cross-linker, or high-dissolution agent;

baking the first positive resist pattern to form a baked resist pattern;

forming a second positive resist layer on the substrate and within the plurality of openings of the baked resist pattern;

exposing the second positive resist layer to form a plurality of exposed resist features and a plurality of unexposed resist features on the substrate; and

forming a second resist pattern by providing a solvent to remove the baked resist pattern and the exposed features, leaving the unexposed features intact.

15. The method of claim 14, wherein the first positive resist pattern is baked to a temperature is from about 100°

C. to about 250°

C.

16. The method of claim 14, wherein the first positive resist pattern is baked to a temperature about 100°

C. to about 250°

C. for about 20 sec to about 200 sec.

17. The method of claim 14, wherein the forming of the second positive resist layer comprises applying a spin-on coating process.

18. The method of claim 17, wherein the applying of the spin-on coating process comprises tuning spin speed to form the second positive resist layer thinner than that of the first positive resist pattern.

19. The method of claim 17, wherein the applying of the spin-on coating process provides the second positive resist layer with a tuned surface tension such that the second positive resist layer is thinner than that of the first positive resist pattern.

20. The method of claim 14, wherein the solvent is a developer solvent.