Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts

• US 20100312942A1
• Filed: 06/09/2009
• Published: 12/09/2010
• Est. Priority Date: 06/09/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Elliott, John C., Blinick, Stephen L., Garcia, Enrique Q.
• Granted Patent: US 7,934,045 B2
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.

Claims

1. An apparatus to control an I/O enclosure, the apparatus comprising:

an I/O enclosure;

a bus module that receives two or more peripheral component interconnect express (“

PCIe”

) sideband signals via one or more PCIe cables, the one or more PCIe cables connected between one or more hosts and the I/O enclosure;

a decode module that determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value, each PCIe sideband signal representing a bit in the bus value, the bus value specifying a command for controlling the I/O enclosure; and

an execution module that executes by way of a processor the specified command to perform control actions on the I/O enclosure.

2. The apparatus of claim 1, wherein the decode module is further configured to decode a sequence of two or more bus values received by the bus module, the sequence of two or more bus values corresponding to a command for controlling the I/O enclosure.

3. The apparatus of claim 2, wherein two or more hosts are connected to the I/O enclosure, and wherein the decode module discards bus value sequences specifying a new command during execution of a previous command.

4. The apparatus of claim 2, wherein a sequence of bus values is defined for each command in a set of commands for controlling the I/O enclosure.

5. The apparatus of claim 4, wherein the set of commands comprises one or more of a command to perform a sequenced reset of a PCIe switch and all I/O adapters (“

Autotimed I/O Tower Total Data Path Reset”

), a command to perform a sequenced reset of all I/O adapters without resetting a PCIe switch (“

Auto-timed Total I/O Slot Reset”

), a command that powers off a PCIe switch and puts all I/O adapters into a standby state (“

I/O tower Data Path Power OFF”

), and a command that powers on a PCIe switch and all I/O adapters (“

I/O tower Data Path Power On”

).

6. The apparatus of claim 1, wherein two or more hosts are connected to the I/O enclosure and wherein the decode module discards bus values specifying a new command during execution of a previous command.

7. The apparatus of claim 1, wherein the bus module is further configured to send an alert back to a host, the alert indicating an operating status of the I/O enclosure.

8. The apparatus of claim 7, wherein the bus module sends an alert to the host in response to one or more of the I/O enclosure not being present, the PCIe cable not being connected, the I/O enclosure not being powered on, and the decode module determining that the bus value is an invalid value.

9. The apparatus of claim 1, wherein the sideband signals comprise two or more of an on/off signal (“

CPWRON”

), a reset signal (“

CPERST#), a wake signal (“

CWAKE#), and a cable present signal (“

CPRSNT#).

10. The apparatus of claim 9, wherein the asserted values of each of the on/off signal (“

CPWRON”

), reset signal (“

CPERST#), and wake signal (“

CWAKE#) comprise bits forming the bus value.

11. The apparatus of claim 10, wherein the cable present signal (“

CPRSNT#) comprises an alert signal utilized by the bus module to send an alert back to a host, the alert indicating an operating status of the I/O enclosure.

12. A system to control an I/O enclosure, the system comprising:

one or more hosts;

at least one processor;

an I/O enclosure connected to each of the one or more hosts via one or more peripheral component interconnect express (“

PCIe”

) cables;

a bus module that receives two or more PCIe sideband signals via the one or more PCIe cables;

a decode module that determines an asserted value of each of the two or more sideband signals and combines the sideband signal asserted values to form a bus value, each PCIe sideband signal representing a bit in the bus value, the bus value specifying a command for controlling the I/O enclosure; and

an execution module that executes by way of the processor the specified command to perform control actions on the I/O enclosure.

13. The system of claim 12, wherein the decode module is further configured to decode a sequence of two or more bus values received by the bus module, the sequence of two or more bus values corresponding to a command for controlling the I/O enclosure.

14. The system of claim 12, further comprising one or more PCIe switches.

15. The system of claim 13, further comprising one or more I/O adapters connected to at least one of the one or more PCIe switches.

16. A computer program product comprising a computer readable storage medium having computer usable program code stored thereon executable to perform operations for controlling an I/O enclosure, the operations of the computer program product comprising:

receiving two or more peripheral component interconnect express (“

PCIe”

) sideband signals via one or more PCIe cables, the one or more PCIe cables connected between one or more hosts and an I/O enclosure;

determining an asserted value of each of the two or more sideband signals and combining the sideband signal asserted values to form a bus value, each PCIe sideband signal representing a bit in the bus value, the bus value specifying a command for controlling the I/O enclosure; and

executing the specified command to perform control actions on the I/O enclosure.

17. The computer program product of claim 16, further comprising decoding a sequence of two or more bus values received by the bus module, the sequence of two or more bus values corresponding to a command for controlling the I/O enclosure.

18. The computer program product of claim 17, wherein two or more hosts are connected to the I/O enclosure, and further comprising discarding bus value sequences that specify a new command during execution of a previous command.

19. The computer program product of claim 17, wherein a sequence of bus values is defined for each command in a set of commands for controlling the I/O enclosure.

20. The computer program product of claim 19, wherein the set of commands comprises one or more of a command to perform a sequenced reset of a PCIe switch and all I/O adapters (“

Autotimed I/O Tower Total Data Path Reset”

), a command to perform a sequenced reset of all I/O adapters without resetting a PCIe switch (“

Auto-timed Total I/O Slot Reset”

), a command that powers off a PCIe switch and puts all I/O adapters into a standby state (“

I/O tower Data Path Power OFF”

), and a command that powers on a PCIe switch and all I/O adapters (“

I/O tower Data Path Power On”

).