Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory

• US 20100312952A1
• Filed: 05/28/2010
• Published: 12/09/2010
• Est. Priority Date: 08/18/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Letourneur, Hervé, Maheshwari, Dinesh, Ramanathan, Dinesh, Gujral, Manoj, Chetia, Alakesh, Smith, Donald W.
• Granted Patent: US 8,060,708 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Claims

1. A memory interface, comprising:

a first controller adapted for coupling to a volatile memory;

a second controller adapted for coupling to a nonvolatile memory; and

circuitry adapted to receive a memory request from a processor and to access data stored in the nonvolatile memory and previously copied to the volatile memory by accessing the volatile memory.

2. The memory interface as recited in claim 1, wherein the volatile memory comprises random access memory (RAM).

3. The memory interface as recited in claim 1, wherein the volatile memory comprises synchronous dynamic random access memory (SDRAM).

4. The memory interface as recited in claim 1, wherein the memory request comprises static random access memory (SRAM) access signals forwarded to a first port of the memory interface

5. The memory interface as recited in claim 1, wherein the memory request is a nonvolatile NOR flash memory request that comprises NOR flash memory read access signals.

6. The memory interface as recited in claim 1, wherein the volatile memory comprises SDRAM and wherein the nonvolatile memory comprises NAND flash memory.

7. The circuit as recited in claim 1, wherein the circuitry adapted to receive and satisfy the memory request is configured to satisfy memory request from the processor to either volatile or non-volatile memory according to predetermined volatile and non-volatile latency and timing requirements.

8. The circuit as recited in claim 1, wherein the memory request comprises static random access memory (SRAM) access signals, and wherein the circuit is configured to satisfy the memory request according to predetermined SRAM volatile memory request latency and timing requirements.

9. The circuit as recited in claim 1, wherein the circuit is further configured to receiving a second memory request and to access data stored in the volatile memory substantially contemporaneous with accessing data in the nonvolatile memory according

10. A memory interface, comprising:

an SDRAM memory controller adapted for coupling to an SDRAM;

a NAND flash memory controller adapted for coupling to a NAND flash memory; and

first circuitry adapted to;

(i) receive a volatile memory request from a first processor and to satisfy the volatile memory request by accessing the SDRAM, and (ii) receive a nonvolatile memory read request from the first processor, and to satisfy the nonvolatile read request by accessing both the NAND flash memory and the SDRAM.

11. The memory interface as recited in claim 10, further comprising:

second circuitry adapted to receive a volatile memory request from a second processor and to satisfy the volatile memory request from the second processor by accessing the SDRAM; and

third circuitry adapted to receive a nonvolatile memory read request from the second processor and to satisfy the nonvolatile read request by accessing the NAND flash memory.

12. The circuit as recited in claim 10, wherein the nonvolatile memory read request comprises NAND flash memory access signals, and wherein the volatile memory read request comprises SRAM access signals.

13. The circuit as recited in claim 10, wherein the first circuitry is configured to satisfy the volatile memory request according to predetermined SRAM volatile memory request latency and timing requirements.

14. The circuit as recited in claim 11, wherein the second circuitry comprises an SRAM/NOR configurable port.

15. The circuit as recited in claim 11, wherein the nonvolatile memory read request from the first processor comprises NOR flash memory read access signals.

16. The circuit as recited in claim 15, wherein the second circuitry is configured to satisfy the nonvolatile memory read request according to predetermined nonvolatile NOR flash memory read request latency and timing requirements.

17. The circuit as recited in claim 11, wherein the volatile memory request from the second processor comprises SDRAM access signals.

18. The circuit as recited in claim 11, wherein the nonvolatile memory read request from the second processor comprises NAND flash memory read access signals.

19. A method for satisfying a NOR flash memory read request, comprising:

receiving the NOR flash memory read request that comprises a NOR flash memory read access signals directed to requested data;

retrieving a block of data including the requested data from a NAND flash memory;

storing the block of data in a random access memory; and

retrieving the requested data from the block of data stored in the random access memory.

20. The method as recited in claim 19, further comprising:

providing the requested data such that predetermined nonvolatile NOR flash memory read request latency and timing requirements are met.