HERMETICALLY-SEALED ELECTRICAL CIRCUIT APPARATUS

• US 20100314149A1
• Filed: 09/29/2009
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Abandoned Application

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Ruben, David A., Mattes, Michael F., Larson, Lary R., Gerrish, Paul F., Fenner, Andreas Armin, Mueller, Tyler, Batchelder, Geoffrey, Malin, Anna J., Tyler, Larry E.
• Application Number:
  US12/569,431
• Publication Number:
  US 20100314149A1
• Time in Patent Office: Days
• US Class Current: 174/50.52
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/818 Bonding techniques
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/11 : Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/041 : Stacked PCBs, i.e. having neither an empty space nor mounted components in between
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base

Abstract

Hermetically-sealed electrical circuit apparatus and methods for constructing such apparatus using one or more seal portions.

Claims

1. An electrical circuit apparatus comprising:

a first portion comprising;

a planar connection surface,

a substrate provided from a wafer, wherein the substrate comprises a substrate surface opposite the planar connection surface, and

at least one side surface extending between the substrate surface and the planar connection surface;

a second portion comprising;

a planar connection surface,

a substrate provided from a wafer, wherein the substrate comprises a substrate surface opposite the planar connection surface, and

at least one side surface extending between the substrate surface and the planar connection surface, wherein the planar connection surface of the first portion is bonded to the planar connection surface of the second portion to foam an interface defining at least one interface edge about the perimeter of the interface between the planar connection surfaces of the first portion and the second portion;

at least one circuit device comprising electrical circuitry, wherein the at least one circuit device is encompassed by at least portions of the first portion and the second portion; and

one or more seal portions covering at least the at least one interface edge of the interface to restrict moisture from ingressing into the apparatus.

2. The apparatus of claim 1, wherein the one or more seal portions comprise deposited material.

3. The apparatus of claim 1, wherein the one or more seal portions comprise a thickness of at least about 1 angstrom.

4. The apparatus of claim 1, wherein the one or more seal portions comprise oxide material.

5. The apparatus of claim 1, wherein the one or more seal portions cover at least a portion of the at least one side surface of the first portion and the at least one side surface of the second portion to restrict moisture from ingressing into the apparatus.

6. The apparatus of claim 1, wherein at least one of the first portion and the second portion further comprises one or more layers formed on the substrate thereof terminating at the connection surface thereof and defining a portion of the at least one side surface thereof, wherein the one or more seal portions cover the portion of the at least one side surface defined by the one or more layers to restrict moisture from ingressing into the apparatus.

7. The apparatus of claim 1, wherein the one or more seal portions at least partially cover the substrate surface of the first portion, the substrate surface of the second portion, the at least one side surface of the first portion, and the at least one side surface of the second portion to restrict moisture from ingressing into the apparatus.

8. The apparatus of claim 1, wherein the connection surface of the first portion defines a larger area than the connection surface of the second portion.

9. The apparatus of claim 1, wherein the substrate of the first portion and the substrate of the second portion each comprise semiconductor substrates.

10. The apparatus of claim 1, wherein the at least one circuit device forms a part of an implantable medical device.

11. The apparatus of claim 1, wherein the first portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the first portion comprise a circuit device of the at least one circuit device.

12. The apparatus of claim 11, wherein the one or more layers of the first portion further comprise contact pads electrically coupled to the circuit device and located at the connection surface, and wherein second portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the second portion further comprise a circuit device of the at least one circuit device and contact pads electrically coupled to the circuit device and located at the connection surface, wherein the contact pads of the first portion are electrically coupled to the contact pads of the second portion to electrically couple the circuit device of the first portion to the circuit device of the second portion.

13. The apparatus of claim 1, wherein at least one of the first portion and the second portion defines a cavity, wherein a circuit device of the at least one circuit device is located within the cavity.

14. The apparatus of claim 1, wherein the apparatus further comprises:

one or more interconnect vias formed in at least one of the first portion and the second portion and terminating at one or more surface contacts at the substrate surface, the connection surface, or the at least one side surface of at least one of the first and second portions; and

at least one electrical interconnect extending from the at least one circuit device to at least one of the one or more interconnect vias.

15. The apparatus of claim 1, wherein the connection surface of the first portion is plasma-enhanced bonded to the connection surface of the second portion.

16. A method of providing at least one electrical circuit apparatus, wherein the method comprises:

providing a first portion, wherein the first portion comprises;

a planar connection surface,

a substrate provided from a wafer, wherein the substrate comprises a substrate surface opposite the planar connection surface, and

at least one side surface extending between the substrate surface and the planar connection surface,

providing a second portion, wherein the second portion comprises;

a planar connection surface,

a substrate provided from a wafer, wherein the substrate comprises a substrate surface opposite the planar connection surface, and

at least one side surface extending between the substrate surface and the planar connection surface,

providing at least one circuit device comprising electrical circuitry;

coupling the planar connection surface of the first portion to the planar connection surface of the second portion to form an interface defining at least one interface edge about the perimeter of the interface between the planar connection surfaces of the first portion and the second portion, wherein the at least one circuit device is encompassed by at least portions of the first portion and the second portion; and

providing one or more seal portions covering at least the at least one interface edge of the interface to restrict moisture from ingressing into the apparatus.

17. The method of claim 16, wherein providing one or more seal portions comprising depositing one or more seal portions.

18. The method of claim 16, wherein the one or more seal portions comprise a thickness of at least about 1 angstrom.

19. The method of claim 16, wherein the one or more seal portions comprise oxide material.

20. The method of claim 16, wherein coupling the planar connection surface of the first portion to the planar connection surface of the second portion comprises oxide bonding the planar connection surface of the first portion to the planar connection surface of the second portion.

21. The method of claim 16, wherein coupling the planar connection surface of the first portion to the planar connection surface of the second portion comprises plasma-enhanced bonding the planar connection surface of the first portion to the planar connection surface of the second portion.

22. The method of claim 16, providing the first portion comprises providing one or more layers formed on the substrate thereof terminating at the connection surface thereof and defining a portion of the at least one side surface thereof, wherein the one or more seal portions cover at least the portion of the at least one side surface defined by the one or more layers to restrict moisture from ingressing into the apparatus to restrict moisture from ingressing into the apparatus.

23. The method of claim 22, providing at least one circuit device comprises forming the at least one circuit within the one or more layers formed on the substrate of the first portion.

24. The method of claim 16, wherein the one or more seal portions at least partially cover each of the substrate surfaces and completely cover the at least one side surfaces of the first portion and the second portion to restrict moisture from ingressing into the apparatus.

25. The method of claim 16, wherein the substrate of the first portion and the substrate of the second portion each comprise semiconductor substrates.

26. The method of claim 16, wherein the at least one circuit device forms a part of an implantable medical device.

27. The method of claim 16, wherein at least one of the first portion and the second portion defines a cavity, wherein a circuit device of the at least one circuit device is located within the cavity.

28. The method of claim 16, wherein the apparatus further comprises:

one or more interconnect vias formed in at least one of the first portion and the second portion and terminating at one or more surface contacts at the substrate surface, the connection surface, or the at least one side surface of at least one of the first and second portions; and

at least one electrical interconnect extending from the at least one circuit device to at least one of the one or more interconnect vias.