SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME

• US 20100314661A1
• Filed: 12/30/2009
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Optodevice Company Limited (Seoul Semiconductor Co., Ltd.)
• Inventors: SAKAI, Shiro
• Granted Patent: US 8,294,183 B2
• Time in Patent Office: Days
• US Class Current: 257/183
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/007 comprising nitride compounds

Abstract

The present invention provides a fabrication method of a semiconductor substrate, by which a planar GaN substrate that is easily separated can be fabricated on a heterogeneous substrate, and a semiconductor device which is fabricated using the GaN substrate. The semiconductor substrate comprises a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and voids formed in the first semiconductor layer under the metallic material layer.

Claims

1. A semiconductor substrate, comprising:

a substrate;

a first semiconductor layer arranged on the substrate;

a metallic material layer arranged on the first semiconductor layer;

a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer; and

voids formed in the first semiconductor layer under the metallic material layer.

2. The semiconductor substrate of claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise the same semiconductor material or different semiconductors material, and the metallic material layer comprises a metallic material having a higher melting point than a heating temperature at which the second semiconductor layer is formed.

3. The semiconductor substrate of claim 1, wherein the metallic material layer comprises an oxide layer.

4. The semiconductor substrate of claim 3, wherein a plurality of holes penetrates the metallic material layer.

5. The semiconductor substrate of claim 2, wherein a plurality of holes penetrates the metallic material layer.

6. The semiconductor substrate of claim 1, wherein the substrate comprises a sapphire substrate or a silicon-based substrate.

7. The semiconductor substrate of claim 1, wherein the metallic material layer comprises a tantalum layer that is at least 5 nm thick, a surface of the tantalum layer comprises tantalum oxide, and an interface between the first semiconductor layer and the tantalum layer comprises tantalum and tantalum oxide.

22. A semiconductor device , comprising:

a first compound semiconductor layer arranged on the second semiconductor layer;

an active layer arranged on the first compound semiconductor layer; and

a second compound semiconductor layer arranged on the active layer,

wherein the first compound semiconductor layer is arranged on the second semiconductor layer of the semiconductor substrate of claim 1.

23. The semiconductor device of claim 22, wherein the semiconductor layer comprises a compound semiconductor of the same class as the first compound semiconductor layer, and the first compound semiconductor layer comprises a different refractive index from the semiconductor layer.

8. A method of fabricating a semiconductor substrate, comprising:

forming a first semiconductor layer on a substrate;

forming a metallic material layer on the first semiconductor layer; and

forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein voids are formed in the first semiconductor layer under the metallic material layer while the second semiconductor layer is formed.

9. The method of claim 8, wherein the metallic material layer comprises a plurality of stripe-shaped portions spaced apart from each other, and

wherein the second semiconductor layer is at least 0.5 times as thick as a width of a first stripe-shaped portion of the metallic material layer.

10. The method of claim 8, wherein the metallic material layer comprises an oxide layer.

11. The method of claim 10, wherein a plurality of holes is formed that penetrates the metallic material layer.

12. The method of claim 9, wherein a plurality of holes penetrates the metallic material layer.

13. The method of claim 8, wherein the second semiconductor layer is formed using a metal organic chemical vapor deposition technique, and while growing the second semiconductor layer, a portion of the first semiconductor layer where the metallic material layer is not formed is grown toward the second semiconductor layer.

14. The method of claim 8, wherein the first semiconductor layer and the second semiconductor layer comprise the same semiconductor material, and the metallic material layer comprise a metallic material having a higher melting point than a heating temperature at which the second semiconductor layer is formed.

15. The method of claim 8, wherein the metallic material layer comprises an oxide layer that forms a mask for the first semiconductor layer, and a plurality of holes is formed that penetrates the metallic material layer comprises through which the first semiconductor layer and the second semiconductor layer are coupled,

wherein the second semiconductor layer is formed using a metal organic chemical vapor deposition technique, and

wherein the first semiconductor layer formed under a portion of the metallic material layer reacts with the metallic material layer and oxygen, and the first semiconductor layer evaporates through the plurality of holes to form voids.

16. The method of claim 8, wherein the metallic material layer comprises a tantalum layer that is at least 5 nm thick, and

wherein after the tantalum layer is formed on the first semiconductor layer, a surface of the tantalum layer comprises tantalum oxide, and an interface between the first semiconductor layer and the tantalum layer comprises tantalum and tantalum oxide.

17. The method of claim 8, wherein the substrate is a sapphire substrate or a silicon-based substrate.

18. The method of claim 8, further comprising separating the substrate from the first semiconductor layer using the voids formed in the first semiconductor layer.

19. The method of claim 18, wherein the substrate is separated by a laser lift-off technique.

20. The method of claim 18, wherein the substrate is separated by a grinding technique.

21. The method of claim 18, wherein the substrate is separated from the first semiconductor layer by twisting.

24. The method of claim 8, further comprising:

forming a first compound semiconductor layer on the second semiconductor layer;

forming an active layer on the first compound semiconductor layer; and

forming a second compound semiconductor layer on the active layer.

25. The method of claim 24, wherein the first semiconductor layer and the second semiconductor layer comprise a compound semiconductor of the same class as the first compound semiconductor layer, and the first compound semiconductor layer comprises a different refractive index from the second semiconductor layer.