STRAINED LDMOS AND DEMOS

• US 20100314670A1
• Filed: 05/27/2010
• Published: 12/16/2010
• Est. Priority Date: 05/27/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Aghoram, Umamaheswari, Denison, Marie, Sridhar, Seetharaman, Pendharkar, Sameer
• Granted Patent: US 8,754,497 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

Claims

1. An integrated circuit containing an extended drain metal oxide semiconductor (MOS) transistor, comprising:

a substrate, said substrate having a first conductivity type;

a drift region of said extended drain MOS transistor, said drift region being located in said substrate, in which said drift region has a second conductivity type opposite from said first conductivity type;

stressor RESURF trenches formed in said drift region, said stressor RESURF trenches being separated by distances between 200 nanometers and 2 microns, in which said stressor RESURF trenches include;

stressor elements in said stressor RESURF trenches, so that said stressor elements have stress greater than 100 megapascals (MPa); and

at least one of;

dielectric liners in said stressor RESURF trenches contacting said drift region, so that said stressor elements are located on said dielectric liners; and

filler elements in gaps of said stressor elements.

2. The integrated circuit of claim 1, in which said stressor elements have compressive stress.

3. The integrated circuit of claim 1, in which said stressor elements have tensile stress.

4. The integrated circuit of claim 1, further including field oxide formed over said drift region at a drain diffused contact region.

5. The integrated circuit of claim 1, in which said stressor elements extend over a top surface of said drift region.

6. The integrated circuit of claim 1, in which said stressor RESURF trenches are configured in at least two rows in said drift region.

7. The integrated circuit of claim 1, in which said stressor RESURF trenches are tapered so that a wide end of each said stressor RESURF trench is at least 20 percent wider than a narrow end of each said stressor RESURF trench.

8. An integrated circuit containing an n-channel extended drain MOS transistor, comprising:

a p-type silicon substrate, said substrate having a (100) orientation;

an n-type drift region of said extended drain MOS transistor, said drift region being located in said substrate;

stressor RESURF trenches formed in said drift region, said stressor RESURF trenches being separated by distances between 200 nanometers and 2 microns, in which said stressor RESURF trenches include;

stressor elements in said stressor RESURF trenches, so that said stressor elements have compressive stress greater than 100 megapascals (MPa); and

at least one of;

dielectric liners in said stressor RESURF trenches contacting said drift region, so that said stressor elements are located on said dielectric liners; and

filler elements in gaps of said stressor elements.

9. The integrated circuit of claim 8, in which said drift region is oriented so that current flow in said drift region is oriented in a <

100>

direction.

10. The integrated circuit of claim 8, in which said drift region is oriented so that current flow in said drift region is oriented in a <

110>

direction.

11. The integrated circuit of claim 8, further including field oxide formed over said drift region at a drain diffused contact region.

12. The integrated circuit of claim 8, in which said stressor elements are formed of silicon oxynitride.

13. The integrated circuit of claim 8, in which said stressor elements are formed of silicon nitride.

14. The integrated circuit of claim 8, in which said stressor elements extend over a top surface of said drift region.

15. An integrated circuit containing a p-channel extended drain MOS transistor, comprising:

an n-type silicon substrate, said substrate having a (100) orientation;

a p-type drift region of said extended drain MOS transistor, said drift region being located in said substrate, so that current flow in said drift region is oriented in a <

110>

direction;

stressor RESURF trenches formed in said drift region, said stressor RESURF trenches being separated by distances between 200 nanometers and 2 microns, in which said stressor RESURF trenches include;

stressor elements in said stressor RESURF trenches, so that said stressor elements have tensile stress greater than 100 megapascals (MPa); and

at least one of;

dielectric liners in said stressor RESURF trenches contacting said drift region, so that said stressor elements are located on said dielectric liners; and

filler elements in gaps of said stressor elements.

16. The integrated circuit of claim 15, in which said stressor RESURF trenches do not extend into a channel region of said extended drain MOS transistor, and do not extend into a drain diffused contact region of said extended drain MOS transistor

17. The integrated circuit of claim 15, in which said stressor RESURF trenches extend through a bottom surface of said drift region and into said substrate.

18. The integrated circuit of claim 15, further including field oxide formed over said drift region at a drain diffused contact region.

19. The integrated circuit of claim 15, in which said stressor elements are formed of silicon nitride.

20. The integrated circuit of claim 15, in which said stressor elements extend over a top surface of said drift region.