Power semiconductor devices integrated with clamp diodes sharing same gate metal pad

• US 20100314681A1
• Filed: 06/11/2009
• Published: 12/16/2010
• Est. Priority Date: 06/11/2009
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Granted Patent: US 8,164,162 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/7397 : and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 : the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/866 : Zener diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12035 : Zener diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Claims

1. A vertical semiconductor power MOSFET device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region with first type conductivity in active area encompassed in a body region with second type conductivity above a drain region disposed on a bottom surface of a low-resistivity substrate with first type conductivity, wherein said trench MOSFET cell further comprising:

an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower doping concentration than the substrate;

a first insulating layer serving as gate oxide lining the inner surface of openings for trench gates;

a second insulating layer functioning as thick oxide interlayer;

a plurality of trench contacts filled with a barrier layer and tungsten plugs;

a source metal layer connected to the source regions and the body regions via trench source-body contacts;

a gate-source clamp diode connected between a first gate metal and a source metal, composed of multiple back-to-back Zener diodes disposed inside of edge termination area;

a gate-drain clamp diode connected between a second gate metal and a first drain metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having said polysilicon Zener diode or said gate metal cross over said edge termination;

said first drain metal connected to the epitaxial layer via trench drain contacts;

a second drain metal layer formed on a bottom surface of the substrate; and

said first and second gate metals connected together through multiple metal stripes with metal gap between two adjacent metal stripes.

2. The MOSFET of claim 1, wherein gate metal runner also serving as metal field plate is deposited over body region in termination area.

3. The MOSFET of claim 1, wherein gate metal runner also serving as metal field plate is deposited over deep guard ring in termination area.

4. The MOSFET of claim 1, wherein implantation regions of said first doping type in top surface of said epitaxial layer next to body region and underneath trench bottom is implemented for Rds reduction.

5. A vertical semiconductor power IGBT device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by an emitter region with first type conductivity in active area encompassed in a base region with second type conductivity, wherein said IGBT cell further comprising:

a substrate heavily doped with the second type conductivity;

a first epitaxial layer grown on the substrate and heavily doped with the first type conductivity;

a second epitaxial layer grown on the first epitaxial layer and lightly doped with the first type conductivity;

a first insulating layer serving as gate oxide lining the inner surface of openings for trench gates;

a second insulating layer functioning as thick oxide interlayer;

a plurality of trench contacts filled with a barrier layer and tungsten plugs;

an emitter metal layer connected to the emitter regions and the base regions via trench emitter-base contacts;

a gate-emitter clamp diode connected between a first gate metal and a emitter metal, composed of multiple back-to-back Zener diodes disposed inside of edge termination area;

a gate-collector clamp diode connected between a second gate metal and a first collector metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having said polysilicon zener diode or said gate metal cross over said edge termination;

said first collector metal connected to the epitaxial layer via trench drain contacts;

a second collector metal layer formed on a bottom surface of the substrate; and

said first and second gate metals connected together through multiple metal stripes with metal gap between two adjacent metal stripes.

7. The IGBT of claim 7, wherein said IGBT is NPT IGBT having a lightly doped substrate with said first type conductivity type instead of said first and second epitaxial layers on said substrate heavily doped with the second type conductivity.

6. The IGBT of claim 7, wherein said IGBT is PT IGBT having said first and second epitaxial layers.

8. The IGBT of claim 7, wherein said IGBT is NPT IGBT having a lightly doped substrate with said first type conductivity type instead of said first and second epitaxial layers, on a substrate alternately heavily doped with said first and second type conductivity which provide a integrated collector shorting diode with IGBT device.

9. The IGBT of claim 7, wherein gate metal runner also serving as metal field plate is deposited over deep guard ring in termination area.