Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions

• US 20100314682A1
• Filed: 03/05/2010
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Guan, Lingpeng, Bhalla, Anup, Chen, John, Yilmaz, Hamza, Lee, Yeeheng, Bobde, Madhur
• Granted Patent: US 8,390,058 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Claims

1. A semiconductor power device comprising:

a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer;

trenches opened in the second semiconductor layer extending vertically to the first semiconductor layer;

a first epitaxial layer of a first conductivity type formed on sidewalls of the trenches; and

a second epitaxial layer formed on the first epitaxial layer;

wherein the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions.

2. The semiconductor power device of claim 1 wherein:

the second epitaxial layer substantially fills a lower portion of gaps not occupied by the first epitaxial layer in at least some of the trenches.

3. The semiconductor power device of claim 2 wherein:

sidewalls of the second epitaxial layer merge together towards the bottom of the trench.

4. The semiconductor power device of claim 1 wherein:

the sidewalls of the trenches are angled to form tapered trenches converging toward a bottom surface of the trenches.

5. The semiconductor power device of claim 1 wherein:

the second epitaxial layer is of a first conductivity type.

6. The semiconductor power device of claim 1 wherein:

the second epitaxial layer is of a second conductivity type or an intrinsic semiconductor material.

7. The semiconductor power device of claim 1 further comprising:

a first dielectric fill in a central gap not occupied by the second epitaxial layer at the center of the trenches.

8. The semiconductor power device of claim 1 further comprising:

a gate electrode disposed in an upper portion of at least some of the trenches.

9. The semiconductor power device of claim 8 further comprising:

a deep dielectric layer under the gate electrode.

10. The semiconductor power device of claim 1 further comprising:

Schottky diodes and PN junction diodes formed between adjacent trenches.

11. The semiconductor power device of claim 10 wherein:

the PN junction diode is a charge injection controlled diode in series connection with a charge injection control resistor and in parallel connection with the Schottky diode.

12. The semiconductor power device of claim 1 wherein:

said second semiconductor layer has a width between two adjacent trenches significantly wider than a width of said first epitaxial layer.

13. The semiconductor power device of claim 1 wherein:

said second semiconductor layer having a width between two adjacent trenches at least about three times wider than a width of said first epitaxial layer.

14. The semiconductor power device of claim 1 wherein:

the semiconductor power device further comprises a MOSFET.

15. The semiconductor power device of claim 1 wherein:

the semiconductor power device further comprises an IGBT.

16. The semiconductor power device of claim 1 wherein:

the semiconductor power device further comprises an IGBT integrated with a diode.

17. The semiconductor power device of claim 1 wherein:

said second semiconductor layer has a graded doping profile, with the doping concentration decreasing from top to bottom.

18. The semiconductor power device of claim 7 further comprising:

a termination structure having a dielectric trench comprising a network of dielectric columns formed from said first dielectric fill and a second dielectric fill formed between said dielectric columns within the network.

19. The semiconductor power device of claim 7 wherein:

at least a second device is disposed on a semiconductor substrate wherein the trenches disposed between adjacent devices have a greater trench width.

20. The semiconductor power device of claim 1 wherein:

the device further comprises transistor cells arranged to have a stripe layout.

21. The semiconductor power device of claim 1 wherein:

the device further comprises transistor cells arranged to have a closed cell layout.

22. The semiconductor power device of claim 1 further comprising:

a termination region comprising an array of termination cells, with a first termination cell at an interface to the active area, wherein each termination cell further comprises;

a mesa of the second semiconductor layer having the first epitaxial layer formed on the sidewalls thereof and the second epitaxial layer formed on the first epitaxial layer, the mesa being adjacent to trenches with a dielectric fill;

a first region of the first conductivity type formed in the top surface of the mesa; and

a second region of the second conductivity type formed in the top surface of the mesa, the second region being spaced apart from the first region in the mesa,

wherein the first region of most termination cells is electrically connected to the second region of an adjacent termination cell.

23. A method of forming a semiconductor power device comprising:

etching trenches in a second semiconductor layer of a second conductivity type;

growing a first epitaxial layer of a first conductivity type in said trenches; and

growing a second epitaxial layer on top of the first epitaxial layer;

wherein a first semiconductor layer of a first conductivity type is provided under said second semiconductor layer and

wherein said first epitaxial layer reaches the first semiconductor layer.

24. The method of claim 23 wherein:

the first epitaxial layer is charge balanced with surrounding semiconductor regions.

25. The method of claim 23 wherein:

growing the second epitaxial layer is done such that the second epitaxial layer substantially fills a lower portion of the trenches.

26. The method of claim 23 further comprising:

filling the remaining gap in the trenches with a dielectric after growing the second epitaxial layer;

27. The method of claim 26 further comprising:

etching back the dielectric and forming a trench gate electrode in a top portion of at least some of the trenches after filling the remaining gap in the trenches with a dielectric.

28. The method of claim 26 further comprising:

simultaneously etching trenches in the termination region while etching said trenches for forming a network of dielectric filled trenches in the termination region with semiconductor mesas left between the dielectric filled trenches; and

etching away the semiconductor mesas in the termination region and filling the space with a second dielectric fill to form a wide and deep dielectric trench in the termination region.

29. A method of forming a dielectric trench comprising:

forming a network of trenches in a semiconductor layer and filling the trenches with a first dielectric to form a network of dielectric columns with semiconductor mesas contained within;

etching away the semiconductor mesas within the network of dielectric columns, and filling the gaps with a second dielectric, thus forming a wide and deep dielectric trench.