CHARGING PROTECTION DEVICE

• US 20100314685A1
• Filed: 06/12/2009
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Buller, James F., Zhou, Jingrong, Wu, David
• Granted Patent: US 8,048,753 B2
• Time in Patent Office: Days
• US Class Current: 257/350
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P⁺ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P⁺-doped substrate contact in the bulk silicon layer of the SOI substrate.

Claims

1. A method comprising:

forming an insulating layer on a bulk silicon substrate;

forming an active silicon layer on the insulating layer;

forming a transistor on the active silicon layer, the transistor including source/drain regions formed in the active silicon layer;

forming a diode on the active silicon layer, the diode including two active regions; and

electrically connecting the drain region, active diode regions, and bulk silicon layer to form a charging protection device.

2. The method according to claim 1, comprising:

forming an interlayer dielectric on the transistor and the diode;

forming first, second, third, and fourth contact holes through the interlayer dielectric;

filling the first, second, third, fourth contact holes with a conductive material to form first, second, third, and fourth conductive contacts; and

forming first and second metal lines on the interlayer dielectric;

wherein the first conductive contact connects the drain region of the transistor with the first metal line, the second conductive contact connects one active region of the diode with the first metal line, the third conductive contact connects the second active region of the diode with the second metal line, and the fourth conductive contact connects the second metal line to the bulk silicon layer.

3. The method according to claim 2, further comprising:

etching a trench in the active silicon layer, prior to forming the inter layer dielectric layer, between the transistor and the diode; and

filling the trench with an insulating material to form a shallow trench isolation region.

4. The method according to claim 3, further comprising introducing a P-type dopant into the bulk silicon substrate.

5. The method according to claim 4, further comprising ion implanting a P⁺-dopant into the bulk silicon substrate through the fourth contact hole, prior to filling the fourth contact hole, to form a substrate contact.

6. The method according to claim 5, further comprising ion implanting boron as the P⁺-dopant.

7. The method according to claim 3, further comprising filling the contact holes with tungsten or polysilicon.

8. The method according to claim 3, further comprising patterning a metal 1 layer to form the first and second metal lines.

9. A semiconductor device comprising:

a silicon-on-insulator (SOI) substrate including a bulk silicon layer;

an active silicon layer on the SOI substrate;

a transistor formed in the active silicon layer, the transistor including source/drain regions; and

a diode formed in the active silicon layer, the diode including two active regions;

wherein, the drain region, active diode regions, and bulk silicon layer are electrically connected to form a charging protection device.

10. The semiconductor device according to claim 9, comprising

first, second, third, and fourth conductive contacts;

and

first and second metal lines;

wherein the first conductive contact connects the drain of the transistor with the first metal line, the second conductive contact connects one active region of the diode with the first metal line, the third conductive contact connects the second active region of the diode with the second metal line, and the fourth conductive contact connects the second metal line to the bulk silicon layer.

11. The semiconductor device according to claim 10, further comprising a shallow trench isolation region between the transistor and the diode.

12. The semiconductor device according to claim 10, wherein the bulk silicon layer is P-doped.

13. The semiconductor device according to claim 12, further comprising a P⁺-doped substrate contact formed in the bulk silicon layer and connected to the fourth conductive contact.

14. The semiconductor device according to claim 13, wherein the transistor is an NMOS transistor.

15. The semiconductor device according to claim 13, wherein the first active region of the diode is N⁺-doped and the second active region is P⁺-doped.

16. The semiconductor device according to claim 13, wherein the first active region of the diode is P⁺-doped and the second active region is N⁺-doped.

17. The semiconductor device according to claim 13, wherein the first, second, third, and fourth conductive contacts comprise tungsten or polysilicon.

18. The semiconductor device according to claim 13, further comprising an interlayer dielectric on the transistor and the diode, wherein the first, second, third, and fourth conductive contacts are formed through the interlayer dielectric and the first and second metal lines are formed on the interlayer dielectric.

19. The semiconductor device according to claim 18, further comprising a metal 1 pattern on the interlayer dielectric, wherein the metal 1 pattern includes the first and second metal lines.

20. A method of fabricating a semiconductor device, the method comprising:

forming an insulating layer on a P-type bulk silicon substrate;

forming an active silicon layer on the insulating layer;

forming a transistor on the active silicon layer, the transistor including source/drain regions formed in the active silicon layer;

forming a diode on the active silicon layer, the diode including two active regions;

etching a trench in the active silicon layer, between the transistor and the diode;

filling the trench with silicon dioxide, wherein a shallow trench isolation region is formed;

forming an interlayer dielectric on the transistor and the diode;

etching first, second, third, and fourth contact holes through the interlayer dielectric;

ion implanting B into the bulk silicon substrate through the fourth contact hole;

depositing tungsten or polysilicon in the first, second, third, fourth contact holes to form first, second, third, and fourth conductive contacts; and

patterning a metal layer to form first and second metal lines on the interlayer dielectric;

wherein the first conductive contact connects the drain region of the transistor with the first metal line, the second conductive contact connects one active region of the diode with the first metal line, the third conductive contact connects the second active region of the diode with the second metal line, and the fourth conductive contact connects the second metal line to the bulk silicon layer.