FARADAY CAGE FOR CIRCUITRY USING SUBSTRATES

• US 20100314726A1
• Filed: 09/29/2009
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Mattes, Michael F., Gerrish, Paul F., Mueller, Tyler, Batchelder, Geoffrey, Malin, Anna J., Tyler, Larry E.
• Granted Patent: US 8,125,058 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/818 Bonding techniques
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/11 : Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/041 : Stacked PCBs, i.e. having neither an empty space nor mounted components in between
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base

Abstract

An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device.

Claims

1. An apparatus comprising:

at least one circuit device comprising electrical circuitry;

a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, the first Faraday cage portion comprising;

a substrate, wherein the substrate is provided from a wafer,

at least one patterned metal layer formed on the substrate providing a part of the first conductive portion of the Faraday cage enclosure,

one or more additional layers formed on the at least one patterned metal layer terminating at a connection surface, wherein the one or more additional layers provide an electrical interconnect connected to the at least one circuit device and extending to a location outside of the Faraday cage enclosure, and

a plurality of conductive vias formed in the one or more additional layers providing a part of the first conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias are in contact with the at least one patterned metal layer and terminate in a via contact at the connection surface of the first Faraday cage portion; and

a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device, the second Faraday cage portion comprising;

a substrate, wherein the substrate is provided from a wafer,

a plurality of conductive vias formed in the substrate corresponding to the plurality of conductive vias of the first Faraday cage portion providing a part of the second conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias of the second Faraday cage portion extend between a connection surface of the substrate of the second Faraday cage portion and a surface of the substrate opposite the connection surface, and

at least one patterned metal layer formed on the surface of the substrate opposite the connection surface of the substrate of the second Faraday cage portion and in electrical contact with the plurality of conductive vias of the second Faraday cage providing a part of the second conductive portion of the Faraday cage enclosure,

wherein the plurality of conductive vias of the first Faraday cage portion and the plurality of conductive vias of the second Faraday cage portion are in electrical connection when the connection surface of the first Faraday cage portion is coupled to the connection surface of the second Faraday cage portion such that the Faraday cage enclosure is formed by the first conductive portion and the second conductive portion.

2. The apparatus of claim 1, wherein the apparatus further comprises one or more interconnect vias formed in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein the electrical interconnect passes through one or more insulated locations of the Faraday cage enclosure to connect to the one or more interconnect vias.

3. The apparatus of claim 1, wherein the plurality of conductive vias formed in the substrate of the second Faraday cage portion comprise vias extending through the substrate.

4. The apparatus of claim 1, wherein the connection surface of the first Faraday cage portion is oxide bonded to the connection surface of the second Faraday cage portion such that the Faraday cage enclosure is formed by the first conductive portion and the second conductive portion.

5. The apparatus of claim 1, wherein the at least one circuit device comprises one or more device contacts, wherein the connection surface of the first Faraday cage portion comprises one or more conductive contact pads connected to the one or more device contacts, wherein the electrical interconnect extends from the one or more conductive contact pads connected to the one or more device contacts to a location outside the Faraday cage enclosure, and further wherein a cavity is defined in the connection surface of the second Faraday cage portion, and further wherein the cavity is sized to receive the circuit device for connection of the one or more device contacts thereof to the one or more conductive contact pads of the first Faraday cage portion.

6. The apparatus of claim 1, wherein the apparatus forms a part of an implantable medical device.

7. A method of providing a Faraday cage enclosure for surrounding at least one circuit device, wherein the at least one circuit device comprises electrical circuitry, wherein the method comprises:

providing a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure, wherein providing the first Faraday cage portion comprises;

providing a wafer substrate,

providing at least one patterned metal layer on the wafer substrate to provide a part of the first conductive portion of the Faraday cage enclosure,

providing one or more additional layers on the at least one patterned metal layer terminating at a connection surface, wherein the one or more additional layers provide an electrical interconnect for connecting the at least one circuit device to a location outside of the Faraday cage enclosure, and

providing a plurality of conductive vias in the one or more additional layers providing a part of the first conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias are in contact with the at least one patterned metal layer and terminate in a via contact at the connection surface of the first Faraday cage portion;

providing a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure, wherein providing the second Faraday cage portion comprises;

providing a wafer substrate,

forming a plurality of conductive vias in the wafer substrate corresponding to the plurality of conductive vias of the first conductive portion to provide a part of the second conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias of the second Faraday cage portion extend between a connection surface of the semiconductor wafer substrate of the second Faraday cage portion and a surface of the wafer substrate opposite the connection surface, and

patterning at least one metal layer formed on the surface of the wafer substrate opposite the connection surface of the wafer substrate of the second Faraday cage and in electrical contact with the plurality of conductive vias of the second Faraday cage providing a part of the second conductive portion of the Faraday cage enclosure; and

bonding the connection surface of the first Faraday cage portion to the connection surface of the second Faraday cage portion such that the via contacts of the plurality of conductive vias of the first Faraday cage portion are in electrical contact with the plurality of conductive vias of the second Faraday cage portion to form the Faraday cage enclosure comprising the first conductive portion and the second conductive portion.

8. The method of claim 7, wherein the method further comprises forming one or more interconnect vias in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein the electrical interconnect passes through one or more insulated locations of the Faraday cage enclosure to connect to the one or more additional interconnect vias.

9. The method of claim 7, wherein forming the plurality of conductive vias in the wafer substrate of the second Faraday cage portion comprises forming vias extending through the wafer substrate.

10. The method of claim 7, wherein bonding the connection surface of the first Faraday cage portion to the connection surface of the second Faraday cage portion comprises using an oxide bond to bond oxide material of the connection surfaces of the first and second Faraday cage portions.

11. The method of claim 7, wherein the at least one circuit device comprises one or more device contacts, wherein the connection surface of the first Faraday cage portion comprises one or more conductive contact pads corresponding to the one or more device contacts of the at least one circuit device, wherein the electrical interconnect extends from the one or more conductive contact pads to a location outside the Faraday cage enclosure, and wherein the method further comprises positioning the at least one circuit device relative to the first Faraday cage portion to electrically connect the one or more device contacts to the one or more conductive contact pads of the first Faraday cage portion, wherein the at least one circuit device is positioned in a cavity defined in the connection surface of the second Faraday cage portion.

12. An apparatus comprising:

at least one circuit device comprising electrical circuitry;

a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, the first Faraday cage portion comprising;

a conductive substrate, wherein the conductive substrate is provided from a wafer, wherein the conductive substrate provides a part of the first conductive portion of the Faraday cage enclosure,

one or more layers formed on the conductive substrate terminating at a connection surface, wherein the one or more layers provide an electrical interconnect connected to the at least one circuit device and extending to a location outside of the Faraday cage enclosure, and

a plurality of conductive vias formed in the one or more layers providing a part of the first conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias are in electrical contact with the conductive substrate and terminate in a via contact at the connection surface of the first Faraday cage portion; and

a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device, the second Faraday cage portion comprising a conductive substrate, wherein the conductive substrate comprises a connection surface and a surface of the conductive substrate opposite the connection surface, wherein the conductive substrate is provided from a wafer, wherein the conductive semiconductor substrate provides the second conductive portion of the Faraday cage enclosure, and further wherein the via contacts of the plurality of conductive vias of the first Faraday cage portion are in electrical contact with conductive portions of the connection surface of the conductive substrate of the second Faraday cage portion such that the Faraday cage enclosure is formed by the first conductive portion and the second conductive portion.

13. The apparatus of claim 12, wherein the apparatus further comprises one or more interconnect vias formed in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein the electrical interconnect passes through one or more insulated locations of the Faraday cage enclosure to connect to the one or more interconnect vias.

14. The apparatus of claim 13, wherein the one or more interconnect vias comprise at least one or more vias extending through the conductive substrate of the second Faraday cage portion terminating at one or more surface contacts formed at the surface of the conductive substrate of the second Faraday cage portion opposite the connection surface.

15. The apparatus of claim 12, the at least one circuit device comprises one or more device contacts, wherein the connection surface of the first Faraday cage portion comprises one or more conductive contact pads connected to the one or more device contacts, wherein the electrical interconnect extends from the one or more conductive contact pads connected to the one or more device contacts to a location outside the Faraday cage enclosure, and further wherein a cavity is defined in the connection surface of the second Faraday cage portion, and further wherein the cavity is sized to receive the circuit device for connection of the one or more device contacts thereof to the one or more conductive contact pads of the first Faraday cage portion.

16. The apparatus of claim 12, wherein the conductive substrate of at least the second Faraday cage portion is provided from a doped semiconductor substrate, and further wherein the connection surface of the first Faraday cage portion is oxide bonded to the connection surface of the second Faraday cage portion such that the Faraday cage enclosure is formed by the first conductive portion and the second conductive portion.

17. The apparatus of claim 12, wherein the at least one circuit device forms a part of an implantable medical device.

18. A method of providing a Faraday cage enclosure for surrounding at least one circuit device, wherein the at least one circuit device comprises electrical circuitry, wherein the method comprises:

providing a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure, wherein providing the first Faraday cage portion comprises;

providing a conductive wafer substrate, wherein the conductive wafer substrate provides a part of the first conductive portion of the Faraday cage enclosure,

providing one or more layers on the conductive wafer substrate terminating at a connection surface, wherein the one or more layers provide an electrical interconnect for connecting the at least one circuit device to a location outside of the Faraday cage enclosure, and

providing a plurality of conductive vias in the one or more layers providing a part of the first conductive portion of the Faraday cage enclosure, wherein each of the plurality of conductive vias are in contact with the conductive wafer substrate and terminate in a via contact at the connection surface of the first Faraday cage portion;

providing a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure, wherein providing the second Faraday cage portion comprises providing a conductive wafer substrate, wherein the conductive wafer substrate comprises a connection surface and a surface of the conductive wafer substrate opposite the connection surface, wherein the conductive wafer substrate provides the second conductive portion of the Faraday cage enclosure; and

bonding the connection surface of the first Faraday cage portion to the connection surface of the second Faraday cage portion such that the via contacts of the plurality of conductive vias of the first Faraday cage portion are in electrical contact with conductive portions of the connection surface of the conductive wafer substrate of the second Faraday cage portion to form the Faraday cage enclosure comprising the first conductive portion and the second conductive portion.

19. The method of claim 18, wherein the at least one circuit device comprises one or more device contacts, wherein the connection surface of the first Faraday cage portion comprises one or more conductive contact pads corresponding to the one or more device contacts of the at least one circuit device, wherein the electrical interconnect extends from the one or more conductive contact pads to a location outside the Faraday cage enclosure, and wherein the method further comprises positioning the at least one circuit device relative to the first Faraday cage portion to electrically connect the one or more device contacts to the one or more conductive contact pads of the first Faraday cage portion, wherein the at least one circuit device is positioned in a cavity defined in the connection surface of the second Faraday cage portion.

20. The method of claim 18, wherein the method further comprises forming one or more interconnect vias in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein the electrical interconnect passes through one or more insulated locations of the Faraday cage enclosure to connect to the one or more interconnect vias.

21. The method of claim 20, wherein forming one or more interconnect vias comprises forming one or more vias extending through the conductive wafer substrate of the second Faraday cage portion terminating at one or more surface contacts formed at the surface of the conductive wafer substrate of the second Faraday cage opposite the connection surface.

22. The method of claim 18, wherein providing the conductive wafer substrate of the second Faraday cage portion comprises providing a doped semiconductor wafer substrate, and further wherein bonding the connection surface of the first Faraday cage portion to the connection surface of the second Faraday cage portion comprises using an oxide bond to bond oxide material of the connection surfaces of the first and second Faraday cage portions.

23. An apparatus comprising:

at least one circuit device comprising electrical circuitry;

a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, the first Faraday cage portion comprising a substrate provided from a wafer, wherein the first Faraday cage portion comprises a connection surface, wherein the connection surface comprises one or more conductive contact portions terminating the first conductive portion of the Faraday cage enclosure and surface portions comprising oxide material;

a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device, the second Faraday cage portion comprising a substrate provided from a wafer, wherein the second Faraday cage portion comprises a connection surface, wherein the connection surface comprises one or more conductive contact portions terminating the second conductive portion of the Faraday cage enclosure and surface portions comprising oxide material, wherein the one or more conductive contact portions of the connection surface of the first Faraday cage portion are aligned with the one or more conductive contact portions of the connection surface of the second Faraday cage portion, and further wherein the oxide material of the connection surface of the first Faraday cage portion is bonded to the oxide material of the connection surface of the second Faraday cage portion to provide a bonded oxide interface therebetween while an electrical connection is provided between the one or more conductive contact portions of the connection surface of the first Faraday cage portion and the one or more conductive contact portions of the connection surface of the second Faraday cage portion to form the Faraday cage enclosure.

24. The apparatus of claim 23, wherein at least one of the first and second conductive portions forming the Faraday cage enclosure comprises one or more through silicon vias.

25. The apparatus of claim 23, wherein the apparatus further comprises:

one or more interconnect vias formed in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein at least one of the one or more interconnect vias comprises a through silicon via formed in at least one of the first and second Faraday cage portions; and

an electrical interconnect extending from one or more conductive contact pads located on one of the connections surfaces of the first and second Faraday cage portions connected to one or more device contacts of the circuit device to a location outside of the Faraday cage enclosure, wherein the electrical interconnect is electrically connected to at least one of the one or more interconnect vias.

26. The apparatus of claim 25, wherein the apparatus further comprises a cavity defined in the connection surface of at least one of the first and second Faraday cage portions, wherein the cavity is sized to receive the circuit device.

27. A method of providing a Faraday cage enclosure for surrounding at least one circuit device, the method comprising:

providing a first Faraday cage portion comprising a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, the first Faraday cage portion comprising a substrate, wherein the first Faraday cage portion comprises a connection surface, wherein the connection surface comprises one or more conductive contact portions terminating the first conductive portion of the Faraday cage enclosure and surface portions comprising oxide material;

providing a second Faraday cage portion comprising a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device, the second Faraday cage portion comprising a substrate, wherein the second Faraday cage portion comprises a connection surface, wherein the connection surface comprises one or more conductive contact portions terminating the second conductive portion of the Faraday cage enclosure and surface portions comprising oxide material;

aligning the one or more conductive contact portions of the connection surface of the first Faraday cage portion with the one or more conductive contact portions of the connection surface of the second Faraday cage portion; and

bonding the oxide material of the connection surface of the first Faraday cage portion to the oxide material of the connection surface of the second Faraday cage portion while providing an electrical connection between the one or more conductive contact portions of the connection surface of the first Faraday cage portion and the one or more conductive contact portions of the connection surface of the second Faraday cage portion to form the Faraday cage enclosure.

28. The method of claim 27, wherein providing at least one of the first and second conductive portions of the first and second Faraday cage portions comprises forming at least one or more through silicon vias.

29. The method of claim 27, wherein providing at least one of the first and second Faraday cage portions comprises:

providing one or more interconnect vias formed in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure and terminating at one or more surface contacts at a surface of at least one of the first and second Faraday cage portions, wherein providing the one or more interconnect vias formed in at least one of the first and second Faraday cage portions outside of the Faraday cage enclosure comprises forming at least one through silicon via in at least one of the first and second Faraday cage portions; and

providing an electrical interconnect extending from one or more conductive contact pads located on one of the connection surfaces of the first and second Faraday cage portions connected to one or more device contacts of the circuit device to a location outside of the Faraday cage enclosure, wherein the electrical interconnect is electrically connected to at least one of the one or more interconnect vias.

30. The method of claim 29, wherein the method further comprises positioning the circuit device in a cavity defined in the connection surface of at least one of the first and second Faraday cage portions.