APPARATUS FOR RESTRICTING MOISTURE INGRESS

• US 20100314733A1
• Filed: 09/29/2009
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Danzl, Ralph B., Mattes, Michael F., Gerrish, Paul F., Mueller, Tyler, Batchelder, Geoffrey, Marrott, Trevor D., Malin, Anna J.
• Granted Patent: US 8,072,056 B2
• Time in Patent Office: Days
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/818 Bonding techniques
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/11 : Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/041 : Stacked PCBs, i.e. having neither an empty space nor mounted components in between
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base

Abstract

Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Claims

1. An electrical circuit apparatus comprising a moisture ingress barrier, wherein the apparatus comprises:

a first portion comprising;

at least one side surface,

a substantially planar connection surface,

a substrate provided from a wafer, and

one or more layers formed on the substrate terminating at the connection surface, wherein at least a portion of the at least one side surface is defined by the one or more layers, wherein the one or more layers comprise;

at least one circuit device comprising electrical circuitry, wherein a perimeter region is defined between the at least one circuit device and the at least one side surface, and

a metallic structure laterally surrounding the at least one circuit device and forming at least part of the moisture ingress barrier, wherein the metallic structure extends from the substrate to the connection surface and is located within the perimeter region; and

a second portion comprising;

at least one side surface,

a substantially planar connection surface, and

a substrate provided from a wafer, wherein at least a portion of the at least one surface is defined by the substrate,

wherein the connection surface of the first portion is bonded to the connection surface of the second portion to form a hermetic interface proximate the metallic structure of the first portion, wherein the hermetic interface forms at least a part of the moisture ingress bather.

2. The apparatus of claim 1, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.

3. The apparatus of claim 1, wherein the second portion comprises a metallic region located at the connection surface, and further wherein the metallic structure of the first portion is metallically bonded to the metallic region of the second portion to form at least part of the hermetic interface.

4. The apparatus of claim 1, wherein a region of the first portion adjacent the metallic structure is covalently bonded to a region of the second portion to form at least part of the hermetic interface.

5. The apparatus of claim 1, wherein the one or more layers of the first portion further comprise at least one electrical interconnect extending from the at least one circuit device to a location in the perimeter region, and wherein the at least one electrical interconnect passes through one or more insulated locations of the metallic structure.

6. The apparatus of claim 1, wherein the apparatus further comprises:

one or more interconnect vias formed in at least one of the first portion and the second portion and terminating at one or more surface contacts at a surface of at least one of the first and second portions, wherein the one or more interconnect vias formed in the first portion are located in the perimeter region; and

at least one electrical interconnect extending from the at least one circuit device to a location in the perimeter region, wherein each of the at least one electrical interconnect is electrically connected to at least one of the one or more interconnect vias, wherein the at least one electrical interconnect passes through one or more insulated locations of the metallic structure to connect to the one or more interconnect vias.

7. The apparatus of claim 1, wherein the at least one circuit device forms a part of an implantable medical device.

8. An electrical circuit apparatus comprising a moisture ingress barrier, wherein the apparatus comprises:

a first portion comprising;

at least one side surface,

a substantially planar connection surface,

a substrate provided from a wafer, and

one or more layers formed on the substrate terminating at the connection surface, wherein at least a portion of the at least one side surface is formed by the one or more layers, wherein the one or more layers comprise;

at least one circuit device comprising electrical circuitry, wherein a perimeter region is defined between the at least one circuit device and the at least one side surface, and

a metallic structure laterally surrounding the at least one circuit device and forming at least part of the moisture ingress barrier, wherein the metallic structure extends from the substrate to the connection surface and is located within the perimeter region; and

a second portion comprising;

at least one side surface,

a substantially planar connection surface,

a substrate provided from a wafer, and

one or more layers formed on the substrate terminating at the connection surface, wherein at least a portion of the at least one side surface is defined by the one or more layers, wherein the one or more layers comprise;

at least one circuit device comprising electrical circuitry, wherein a perimeter region is defined between the at least one circuit device and the at least one side surface, and

a metallic structure laterally surrounding the at least one circuit device and forming at least part of the moisture ingress barrier, wherein the metallic structure extends from the substrate to the connection surface and is located within the perimeter region,

wherein the connection surface of the first portion is bonded to the connection surface of the second portion to form a hermetic interface proximate the metallic structures of the first and the second portions, wherein the hermetic interface forms at least part of the moisture ingress barrier.

9. The apparatus of claim 8, wherein the metallic structure of the first portion is metallically bonded to the metallic structure of the second portion to form at least part of the hermetic interface.

10. The apparatus of claim 8, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.

11. The apparatus of claim 8, wherein the one or more layers of the first portion further comprise at least one electrical interconnect extending from the at least one circuit device to a location in the perimeter region, and wherein the at least one electrical interconnect passes through one or more insulated locations of the metallic structure.

12. The apparatus of claim 8, wherein the apparatus further comprises:

one or more interconnect vias formed in the perimeter region of at least one of the first and second portions and terminating at one or more surface contacts at a surface of at least one of the first and second portions; and

at least one electrical interconnect extending from one or more circuit devices of the at least one circuit device of the first portion and the at least one circuit device of the second portion to a location in the perimeter region of at least one of the first and second portions, wherein each of the at least one electrical interconnect is electrically connected to at least one of the one or more interconnect vias, wherein the at least one electrical interconnect passes through one or more insulated locations of the metallic structures of the first portion and second portion to connect to the one or more interconnect vias.

13. The apparatus of claim 8, wherein the at least one circuit device of the first portion and the at least one circuit device of the second portion form a part of an implantable medical device.

14. A method of providing at least one electrical circuit apparatus comprising a moisture ingress barrier, wherein the method comprises:

providing a first portion, wherein the first portion comprises a substantially planar connection surface, wherein providing the first portion comprises;

providing a wafer substrate, and

providing one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers comprise;

at least one circuit device comprising electrical circuitry, wherein a perimeter region is defined laterally surrounding the at least one circuit device, and

at least one metallic structure laterally surrounding the at least one circuit device and forming at least part of the moisture ingress barrier of the at least one electrical circuit apparatus, wherein the at least one metallic structure extends from the substrate to the connection surface and is located within the perimeter region; and

providing a second portion, wherein the second portion comprises a substantially planar connection surface, wherein providing the second portion comprises providing a wafer substrate; and

coupling the connection surface of the first portion to the connection surface of the second portion to form at least one hermetic interface proximate the at least one metallic structure of the first portion, wherein the at least one hermetic interface forms at least part of the moisture ingress barrier of the at least one electrical circuit apparatus.

15. The method of claim 14, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.

16. The method of claim 14, wherein providing the second portion further comprises providing at least one metallic region located at the connection surface of the second portion, and wherein coupling the connection surface of the first portion to the connection surface of the second portion to form the at least one hermetic interface comprises metallically bonding the at least one metallic structure of the first portion to the at least one metallic region of the second portion to form at least a part of the at least one hermetic interface.

17. The method of claim 14, wherein coupling the connection surface of the first portion to the connection surface of the second portion to form the at least one hermetic interface comprises covalently bonding at least one region of the first portion adjacent the at least one metallic structure to at least one region of the second portion to form the at least a part of the at least one hermetic interface.

18. The method of claim 14, wherein providing the first portion further comprises providing at least one electrical interconnect formed in the one or more layers of the first portion and extending from the at least one circuit device to a location within the perimeter region, wherein the at least one electrical interconnect passes through one or more insulated locations of the at least one metallic structure.

19. The method of claim 14, wherein providing the second portion further comprises:

providing one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers comprise;

at least one circuit device comprising electrical circuitry, wherein a perimeter region is defined laterally surrounding each of the at least one circuit device, and

at least one metallic structure laterally surrounding the at least one circuit device and forming at least part of the moisture ingress barrier of the at least one electrical circuit apparatus, wherein the at least one metallic structure extends from the substrate to the connection surface and is located within the perimeter region, and

wherein coupling the connection surface of the first portion to the connection surface of the second portion comprises metallically bonding the at least one metallic structure of the first portion to the metallic structure of the second portion to form at least part of the hermetic interface.