HERMETICITY TESTING

• US 20100315110A1
• Filed: 09/29/2009
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Ruben, David A., Larson, Lary R., Gerrish, Paul F., Fenner, Andreas Armin, Mueller, Tyler, Batchelder, Geoffrey, Marrott, Trevor D., Malin, Anna J.
• Granted Patent: US 7,902,851 B2
• Time in Patent Office: Days
• US Class Current: 324/750.24
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/818 Bonding techniques
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/11 : Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/041 : Stacked PCBs, i.e. having neither an empty space nor mounted components in between
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base

Abstract

Electrical circuit apparatus and methods including hermeticity testing structures for testing the hermeticity of the electrical circuit apparatus.

Claims

1. An electrical circuit apparatus comprising:

a first portion comprising a first chain-structure portion of a testing structure, the first portion comprising;

a substantially-planar connection surface,

a substrate provided from a wafer, and

one or more chain-structure segments forming at least a part of the first chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads;

a second portion comprising a second chain-structure portion of the testing structure, the second portion comprising;

a substantially-planar connection surface,

a substrate provided from a wafer, and

one or more chain-structure segments forming at least a part of the second chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads; and

one or more circuit devices comprising electrical circuitry, wherein the one or more circuit devices are located in one or more hermetically-sealed regions,

wherein the connection surface of the first portion is bonded to the connection surface of the second portion, wherein each connection pad of one or more chain-structure segments of the first portion is electrically coupled to a connection pad of the one or more chain-structure segments of the second portion to form the testing structure, wherein the testing structure comprises at least one series circuit extending from a first end to a second end around the one or more hermetically-sealed regions and formed at an interface of the connection surface of the first portion and the connection surface of the second portion.

2. The apparatus of claim 1, wherein the first portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the first portion comprise each chain-structure segment of the first portion, and wherein the second portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the second portion comprise each chain-structure segment of the second portion.

3. The apparatus of claim 2, wherein the one or more layers of at least the first portion further comprise a circuit device of the one or more circuit devices.

4. The apparatus of claim 3, wherein the one or more layers of the first portion further comprise contact pads electrically coupled to the circuit device and located at the connection surface, and wherein the one or more layers of the second portion further comprise a circuit device of the one or more circuit devices and contact pads electrically coupled to the circuit device and located at the connection surface, wherein the contact pads of the first portion are electrically coupled to the contact pads of the second portion to electrically couple the circuit device of the first portion to the circuit device of the second portion.

5. The apparatus of claim 2, wherein the one or more layers of at least the first portion define a cavity, wherein a circuit device of the one or more circuit devices is located within the cavity.

6. The apparatus of claim 1, wherein at least one of the first portion and the second portion comprises at least two interconnects extending to an outer surface of either the first portion or the second portion, wherein one of the at least two interconnects is electrically coupled to the testing structure at the first end of the electrical series and one of the at least two interconnects is electrically coupled to the testing structure at the second end of the electrical series.

7. The apparatus of claim 1, wherein the testing structure forms at least two series circuits interleaved with each other.

8. The apparatus of claim 1, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.

9. The apparatus of claim 1, wherein the one or more circuit devices form a part of an implantable medical device.

10. A method of forming an electrical circuit apparatus, wherein the method comprises:

providing a first portion comprising a first chain-structure portion of a testing structure and a substantially-planar connection surface, wherein providing the first portion comprises;

providing a substrate provided from a wafer, and

providing one or more chain-structure segments, wherein the one or more chain-structure segments faun at least a part of the first chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads;

providing a second portion comprising a second chain-structure portion of the testing structure and a substantially-planar connection surface, wherein providing the second portion comprises;

providing a substrate provided from a wafer, and

providing one or more chain-structure segments, wherein the one or more chain-structure segments form at least a part of the second chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads;

providing one or more circuit devices comprising electrical circuitry, wherein the one or more circuit devices are located in one or more hermetically-sealed regions; and

bonding the connection surface of the first portion to the connection surface of the second portion, wherein each connection pad of one or more chain-structure segments of the first portion is electrically coupled to a connection pad of the one or more chain-structure segments of the second portion to form the testing structure, wherein the testing structure comprises at least one series circuit extending from a first end to a second end around the one or more hermetically-sealed regions and formed at an interface of the connection surface of the first portion and the connection surface of the second portion.

11. The method of claim 10, wherein providing the first portion further comprises forming one or more layers on the substrate terminating at the connection surface, wherein the one or more layers of the first portion comprise each chain-structure segment of the first portion, and wherein providing the second portion further comprises forming one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the second portion comprise each chain-structure segment of the second portion.

12. The method of claim 10, wherein providing the first portion and the second portion further comprises forming at least two interconnects extending to an outer surface of either the first portion or the second portion, wherein one of the at least two interconnects is electrically coupled to the testing structure at the first end of the electrical series and one of the at least two interconnects is electrically coupled to the testing structure at the second end of the electrical series.

13. The method of claim 10, wherein the testing structure forms at least two series circuits interleaved with each other.

14. The method of claim 10, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.

15. A method of testing an electrical circuit apparatus, wherein the method comprises:

providing an electrical circuit apparatus comprising;

a first portion comprising a first chain-structure portion of a testing structure, the first portion comprising;

a substantially-planar connection surface,

a substrate provided from a wafer, and

one or more chain-structure segments forming at least a part of the first chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads,

a second portion comprising a second chain-structure portion of the testing structure, the second portion comprising;

a substantially-planar connection surface,

a substrate provided from a wafer, and

one or more chain-structure segments forming at least a part of the second chain-structure portion, each chain-structure segment comprising;

two connection pads exposed at the connection surface, and

an electrical interconnect electrically coupling the two connection pads, and

one or more circuit devices comprising electrical circuitry formed, wherein the one or more circuit devices define one or more hermetically-sealed regions,

wherein the connection surface of the first portion is bonded to the connection surface of the second portion, wherein each connection pad of one or more chain-structure segments of the first portion is electrically coupled to a connection pad of the one or more chain-structure segments of the second portion to form the testing structure, wherein the testing structure comprises at least one series circuit extending from a first end to a second end around the one or more hermetically-sealed regions and formed at an interface of the connection surface of the first portion and the connection surface of the second portion; and

testing the at least one series circuit of the testing structure to confirm or validate hermeticity about the one or more hermetically-sealed areas.

16. The method of claim 15, wherein testing the at least one series circuit of the testing structure comprises determining if the at least one series circuit is open.

17. The method of claim 15, wherein the testing structure comprises at least two series circuits interleaved with each other, wherein testing the at least one series circuit of the testing structure comprises determining if a first series circuit of the at least two series circuits is shorted to a second series circuit of the at least two series circuits.

18. The method of claim 15, wherein the first portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the first portion comprise each chain-structure segment of the first portion, and wherein the second portion further comprises one or more layers formed on the substrate terminating at the connection surface, wherein the one or more layers of the second portion comprise each chain-structure segment of the second portion.

19. The method of claim 15, wherein one or both of the first portion or the second portion comprises at least two interconnects extending to an outer surface of either the first portion or the second portion, wherein one of the at least two interconnects is electrically coupled to the testing structure at the first end of the electrical series and one of the at least two interconnects is electrically coupled to the testing structure at the second end of the electrical series.

20. The method of claim 15, wherein the substrate of the first portion and the substrate of the second portion comprise semiconductor substrates.