POWER-UP CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

• US 20100315133A1
• Filed: 06/30/2009
• Published: 12/16/2010
• Est. Priority Date: 06/16/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Khil-Ohk
• Granted Patent: US 8,035,428 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: H03K 17/20 Modifications for resetting core switching units to a predetermined state

Abstract

A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.

Claims

1. A power-up circuit for a semiconductor memory device, comprising:

a voltage division unit configured to divide a power supply voltage;

a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal; and

a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.

2. The power-up circuit of claim 1, wherein the voltage division unit comprises a plurality of resistors connected in series between a power supply voltage terminal and a ground voltage terminal to divide the power supply voltage by the resistors.

3. The power-up circuit of claim 2, wherein the voltage division unit generates at least first and second divided voltages having different voltage levels.

4. The power-up circuit of claim 3, wherein the voltage level of the first divided voltage is relatively higher than the voltage level of the second divided voltage.

5. The power-up circuit of claim 1, wherein the first power-up generation unit comprises:

a first transistor configured to receive a ground voltage as a gate voltage; and

a second transistor configured to receive the first divided voltage as a gate voltage, the first transistor and the second transistor being connected in series between a power supply voltage terminal and a ground voltage terminal.

6. The power-up circuit of claim 5, wherein the first transistor comprises a PMOS transistor.

7. The power-up circuit of claim 5, wherein the second transistor comprises an NMOS transistor.

8. The power-up circuit of claim 5, wherein the first power-up generation unit further comprises an inverter configured to invert a detected level outputted by the driving of the first and second transistors.

9. The power-up circuit of claim 1, wherein the second power-up generation unit comprises:

a first detection unit configured to detect the voltage level of the first divided voltage;

a second detection unit configured to detect the voltage level of the second divided voltage; and

a driving unit configured to be driven by the detected levels of the first and second detection units.

10. The power-up circuit of claim 9, wherein the first detection unit comprises:

a third transistor configured to receive a ground voltage as a gate voltage; and

a fourth transistor configured to receive the first divided voltage as a gate voltage, the third transistor and the fourth transistor being connected in series between a power supply voltage terminal and a ground voltage terminal.

11. The power-up circuit of claim 9, wherein the second detection unit comprises:

a fifth transistor configured to receive a ground voltage as a gate voltage; and

a sixth transistor configured to receive the first divided voltage as a gate voltage, the fifth transistor and the sixth transistor being connected in series between a power supply voltage terminal and a ground voltage terminal.

12. The power-up circuit of claim 9, wherein the driving unit comprises:

a first driving unit configured to be driven by the detected levels of the first and second detection units;

a latch unit configured to latch an output of the first driving unit; and

a second driving unit configured to be driven by an output of the latch unit.

13. The power-up circuit of claim 12, wherein the first driving unit comprises:

a first inverter configured to invert the detected level of the first detection unit;

a seventh transistor configured to receive an output of the first inverter as a gate voltage;

a second inverter configured to invert the detected level of the second detection unit; and

an eighth transistor configured to receive an output of the second inverter as a gate voltage.

14. The power-up circuit of claim 13, wherein the seventh and eighth transistors comprise a MOS transistor.

15. The power-up circuit of claim 12, wherein the latch unit has two inverters that are each connected at its input to an output of the other one.

16. A power-up circuit, comprising:

a voltage division unit configured to divide a power supply voltage;

a first detection unit configured to detect a voltage level of a first divided voltage outputted from the voltage division unit to generate a first power-up signal;

a second detection unit configured to detect the voltage level of the first divided voltage outputted from the voltage division unit;

a third detection unit configured to detect a voltage level of a second divided voltage output from the voltage division unit;

a control unit configured to control the first and second detection voltages of the second and third detection units;

a latch unit configured to latch an output of the control unit; and

a driving unit configured to be driven by an output of the latch unit to generate a second power-up signal.

17. The power-up circuit of claim 16, wherein the voltage level of the first divided voltage is relatively higher than the voltage level of the second divided voltage.

18. The power-up circuit of claim 16, wherein the control unit comprises:

a first inverter configured to invert the detected level of the second detection unit;

a transistor configured to receive an output of the first inverter as a gate voltage;

a second inverter configured to invert the detected level of the third detection unit; and

a transistor configured to receive an output of the second inverter as a gate voltage.

19. The power-up circuit of claim 16, wherein the latch unit has two inverters that are each connected at its input to an output of the other one.

20. A power-up circuit for a semiconductor memory device, the power-up circuit comprising:

a first power-up generation unit configured to detect a voltage level of a first divided voltage during an initial stage of applying a power supply to generate a first power-up signal;

a second power-up generation unit configured to detect a voltage level of a second divided voltage, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal;

a first internal circuit configured to control an internal operation to be performed by the first power-up signal generated from the first power-up generation unit; and

a second internal circuit configured to reset an internal operation in response to the second power-up signal generated from the second power-up generation unit.

21. The power-up circuit of claim 20, wherein the voltage level of the first divided voltage is relatively higher than the voltage level of the second divided voltage.