PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME

• US 20100315866A1
• Filed: 12/18/2009
• Published: 12/16/2010
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Se Ho, PARK, Hae Chan
• Granted Patent: US 8,351,240 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Claims

1. A phase change memory device comprising:

variable resistors configured to change into set and reset states in response to an applied current; and

shifting units coupled to the variable resistors such that the shifting units are configured to shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

2. The phase change memory device of claim 1, wherein the shifting unit comprises a plurality of switching elements connected in series.

3. The phase change memory device of claim 2, wherein the switching elements comprises diodes.

4. The phase change memory device of claim 2, wherein the switching elements comprises transistors.

5. The phase change memory device of claim 2, wherein the shifting unit is configured to vary a current path in the shifting unit by a plurality of control signals selectively enabled.

6. The phase change memory device of claim 5, further comprising a plurality of word lines each of which transmits the plurality of control signals.

7. The phase change memory device of claim 6, further comprising a control block configured to select one of the word lines.

8. The phase change memory device of claim 7, wherein the control block includes:

a decoding unit configured to selectively supply enabled control signals and disabled control signals to the word lines; and

switches connected to the word lines and configured to transmit the control signals to the word lines.

9. The phase change memory device of claim 8, wherein each switch is a transistor.

10. The phase change memory device of claim 1, further comprising bit lines coupled to the variable resistors, wherein a current is supplied to the variable resistors through the bit lines.

11. The phase change memory device of claim 1, wherein each variable resistor includes a phase change material.

12. A phase change memory device comprising:

a cell array including a plurality of memory cells, wherein the memory cell includes;

first switching elements connected to first word lines;

second switching elements connected between the first switching elements and second word lines; and

variable resistors connected between the first switching elements and bit lines.

13. The phase change memory device of claim 12, wherein the first and second switching elements have a threshold voltage.

14. The phase change memory device of claim 13, wherein the first and second switching elements are diodes.

15. The phase change memory device of claim 14, wherein each variable resistor is connected to an anode of a first diode of the first switching element,

a cathode of the first diode of the first switching element is connected to anode a second diode of the second switching element and connected to one of the first word lines, and

a cathode of a second diode of the second switching element is connected to one of the second word lines.

16. The phase change memory device of claim 12, wherein the first and second word lines are configured to be selectively grounded or floated.

17. The phase change memory device of claim 12, further comprising switches configured to selectively drive the first and second word lines.

18. The phase change memory device of claim 17, wherein the switches are installed to correspond to each of the first and second word lines.

19. A phase change memory device comprising:

a cell array that includes a plurality of memory cells including first and second word lines intersecting bit lines; and

a control block arranged outside the cell array and configured to control the bit lines and the word lines;

wherein the memory cell includes variable resistors connected to the bit lines and shifting units connected to the variable resistors and the shifting units are configured to be controlled by the first and second word lines.

20. The phase change memory device of claim 19, wherein each shifting unit is configured to shift the resistance distribution of a set state and a reset state of the variable resistor by a predetermined level.

21. The phase change memory device of claim 20, wherein each shifting unit comprises first and second switching elements that are connected in series.

22. The phase change memory device of claim 21, wherein each switching element is a diode.

23. The phase change memory device of claim 22, wherein the first word line is connected to a cathode of a first diode of each shifting unit, and

the second word line is connected to a cathode of a second diode of each shifting unit such that the second word line is configured to vary a current path in each shifting unit.

24. The phase change memory device of claim 19, wherein the control block includes:

a row control block configured to control the word lines; and

a column control block configured to control the bit lines.

25. The phase change memory device of claim 24, wherein the row control block includes:

a first row control block configured to control the first word line; and

a second row control block configured to control the second word line.

26. The phase change memory device of claim 25, wherein each of the first and second row control blocks includes:

a decoding unit configured to select one of the plurality of first or second word lines to supply a ground voltage; and

a switch array configured to selectively supply the ground voltage to the selected word line.

27. The phase change memory device of claim 25, wherein the first row control block is arranged at one side of the cell array substantially perpendicular to the first and second word lines, and

the second row control block is arranged at an opposing side of the cell array relative to where the first row control block is arranged, the second row control block is also substantially perpendicular to the first and second word lines.

28. The phase change memory device of claim 24, wherein the column control block includes:

a first column control block configured to control odd numbered bit lines; and

a second column control block configured to control even numbered bit lines,

wherein the cell array is arranged between the first and second column control blocks such that the first and second column control blocks face each other.

29. The phase change memory device of claim 20, wherein the shifting units comprise transistors connected in series.

30. The phase change memory device of claim 19, wherein each of the variable resistor includes a phase change material.

31. A phase change memory device comprising:

a semiconductor substrate having peripheral areas and a cell area therebetween;

first and second word line select switches on an upper part of the semiconductor substrate in the peripheral areas;

first word lines electrically connected to the first word line select switches, the first word lines on the upper part of the semiconductor substrate on which the first word line select switches are formed;

first diodes on the upper parts of the first word lines;

second word lines on the upper parts of the first diodes;

second diodes on the upper parts of the second word lines correspondingly aligned over the first diodes;

heating electrodes correspondingly coupled to upper parts of the second diodes;

phase change patterns correspondingly coupled to upper parts of the heating electrodes; and

bit lines correspondingly coupled to upper parts of the phase change patterns.

32. The phase change memory device of claim 31, wherein the first and second word line select switches are MOS transistors.

33. The phase change memory device of claim 31, further comprising:

a first insulating layer interposed on the semiconductor substrate on which the first and second word line select switches are formed;

a second insulating layer interposed between the first word line and the second word line;

a third insulating layer interposed between the second word line and the heating electrode; and

a fourth insulating layer interposed between the heating electrode and the bit line.

34. The phase change memory device of claim 31, wherein at least one of the first and second word lines comprises a silicon containing a conductive material.

35. The phase change memory device of claim 34, wherein at least one of the first and second pn diodes is a silicon base schottky diode.

36. The phase change memory device of claim 31, wherein at least one of the first and second word lines comprises a metal containing material.

37. The phase change memory device of claim 36, wherein the first or second pn diodes are metal schottky diodes.

38. The phase change memory device of claim 31, wherein a lower part of the first word line is formed with devices configuring peripheral circuits.

39. A method of driving a phase change memory device that includes variable resistors that reversibly interchange into set and reset states in response to a current applied from bit lines, shifting units connected to the variable resistors and exhibits shift resistance distribution in the set and reset states of the variable resistors by a predetermined level, and memory cells that include a plurality of word lines controlling the shifting units, the method of driving a phase change memory comprising:

when writing and reading the memory cells,

selecting and grounding one of the word lines, and

supplying a writing and reading voltage via the bit lines to remaining word lines in a floating state.

40. The method of driving a phase change memory device of claim 39, further comprising:

when writing the memory cell, sequentially grounding the word lines to shift a set and reset resistance distribution of the variable resistor.

41. The method of driving a phase change memory device of claim 39, further comprising:

when writing the memory cell, applying read voltages having different levels of a holding voltage or less that a threshold voltage through the bit lines to determine each level based on the applied read voltage, wherein the applied read voltage does not cause the variable resistor to change solid state phases.

42. The method of driving a phase change memory device of claim 39, further comprising:

when reading the memory cell,

applying a first read voltage corresponding to a holding voltage or less then a threshold voltage through the bit lines to divide the variable resistors into a set group and a reset group such that the first read voltage does not cause the variable resistors to change solid state phases;

when divided the variable resistors into the set group, applying a second read voltage through the bit line to divide a detailed set state wherein the second read voltage having a lower voltage than the first read voltage; and

when divided the variable resistors into the reset group, applying a third read voltage through the bit line to divide the detailed reset state wherein the third read voltage having a larger voltage than the first read voltage.

43. The method of driving a phase change memory device of claim 42, wherein dividing the set group and the reset group and dividing the detailed set and reset state are performed when different word lines are grounded.

44. A method of driving a phase change memory device that includes bit lines, variable resistors that are electrically connected to the bit lines, first switching elements that are connected to the variable resistors, second switching elements that are electrically connected to the first switching elements, and memory cells including first word lines that control the first switching elements and second word lines that control second switching elements, the method of driving a phase change memory comprising:

when writing the memory cells, grounding the first word lines and writing a first set state and a first reset state by applying a set voltage and a reset voltage preset via the bit lines the second word lines are floating, and

floating the first word line and writing a second set state and a second reset state by applying the set voltage and the reset voltage via the bit lines when the second word lines are grounded.

45. The method of driving a phase change memory device of claim 44, further comprising:

when reading the memory cell, applying first to third read voltages having different levels than a holding voltage or less than a threshold voltage while not causing the variable resistors to change phase, such that the first to third read voltages are applied through the bit lines to determine each level based on the input read voltage.

46. The method of driving a phase change memory device of claim 44, further comprising:

when reading the memory cell, applying a first read voltage of a holding voltage or less that is a threshold voltage through the bit lines to divide a set group and a reset group while not causing the variable resistors to change phase;

when being divided into the set group, applying a second read voltage having a voltage lower than the first read voltage through the bit line to divide a detailed set state; and

when being divided into the reset group, applying a third read voltage having a larger voltage than that of the first read voltage through the bit line to divide a detailed reset state.

47. The method of driving a phase change memory device of claim 46, wherein the dividing the set group and the reset group and the dividing the detailed set and reset state are performed when different word lines are grounded.

48. The method of driving a phase change memory device of claim 47, wherein dividing the set group and the reset group grounds the first word line and floats the second word line.

49. The method of driving a phase change memory device of claim 48, wherein dividing the detailed set state and reset state floats the first word line and grounds the second word line.

50. The method of driving a phase change memory device of claim 46, wherein the third read voltage is positioned in a range that is larger than the holding voltage and smaller than a phase change maximum voltage.