REMOTE PLASMA PROCESSING OF INTERFACE SURFACES

• US 20100317198A1
• Filed: 07/31/2009
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Abandoned Application

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Varadarajan, Seshasayee, Sriram, Mandyam, van Schravendijk, Bart, Antonelli, George Andrew, Buckalew, Bryan L., Rangarajan, Vishwanathan, Xavier, Tony, O' Loughlin, Jennifer
• Application Number:
  US12/533,960
• Publication Number:
  US 20100317198A1
• Time in Patent Office: Days
• US Class Current: 438/758
• CPC Class Codes: C23C 16/0245 by etching with a plasma
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/67201 characterized by the construction of the load-lock chamber
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock.

Claims

1. A semiconductor processing apparatus, comprising:

a processing chamber;

a load lock coupled to the processing chamber via a transfer port;

a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock; and

a remote plasma source configured to provide a remote plasma to the load lock.

2. The semiconductor processing apparatus of claim 1, wherein the processing chamber is a PECVD processing chamber, and wherein the load lock is an inbound load lock.

3. The semiconductor processing apparatus of claim 2, wherein the PECVD processing chamber is configured to deposit an etch stop film.

4. The semiconductor processing apparatus of claim 2, wherein the PECVD processing chamber is configured to deposit an ashable hard mask film.

5. The semiconductor processing apparatus of claim 1, wherein the remote plasma source comprises an outlet configured to direct a flow of remote plasma in a direction normal to a wafer-supporting surface of the wafer pedestal.

6. The semiconductor processing apparatus of claim 5, wherein the remote plasma source outlet has a diameter equal to or larger than a diameter of a wafer for which the load lock is configured for use.

7. The semiconductor processing apparatus of claim 1, further comprising a wafer heater configured to heat a wafer positioned on the wafer pedestal.

8. The semiconductor processing apparatus of claim 1, further comprising an ion filter configured to filter ions from the remote plasma.

9. The semiconductor processing apparatus of claim 8, wherein the ion filter comprises one or more of a charged mesh, a charged wall, and an electron source.

10. The semiconductor processing apparatus of claim 9, wherein the ion filter comprises a plate disposed across an outlet of the remote plasma source, and wherein the plate comprises a plurality of openings each having a length to diameter ratio of 3 or more.

11. The semiconductor processing apparatus of claim 1, wherein the load lock is an outbound load lock.

12. The semiconductor processing apparatus of claim 11, wherein the processing chamber is a low-k dielectric material deposition chamber.

13. The semiconductor processing chamber of claim 1, wherein the processing chamber is a plating chamber, and wherein the load lock is an inbound load lock.

14. A load lock for a semiconductor processing apparatus, the load lock comprising:

an atmospheric transfer port and a chamber transfer port;

a wafer pedestal disposed in an interior of the load lock and configured to support a wafer in the load lock;

a wafer heater configured to heat a wafer in the load lock;

a remote plasma source coupled to the load lock, the remote plasma source comprising an outlet configured to direct a flow of a remote plasma in a direction normal to a wafer supporting surface of the wafer pedestal; and

an ion filter configured to remove ions from remote plasma flowing from the remote plasma source toward the wafer pedestal.

15. The load lock of claim 14, wherein the outlet of the remote plasma source comprises a diameter equal to or greater than a diameter of a wafer for which the load lock is intended for use.

16. The load lock of claim 14, wherein the ion filter comprises a plate disposed across an outlet of the remote plasma source, the plate comprising a plurality of openings each having a length to diameter ratio of 3 or greater.

17. The load lock of claim 14, wherein the ion filter comprises one or more of a charged conductive mesh, a charged wall, and an electron source.

18. The load lock of claim 14, wherein the remote plasma source comprises an inductively coupled plasma source.

19. In a semiconductor processing apparatus, a method of forming an etch stop layer over a wafer with a surface comprising a metal region and a dielectric material region, the method comprising:

inserting the wafer into an inbound load lock that is coupled to a plasma enhanced chemical vapor deposition chamber;

heating the wafer in the load lock;

flowing a remote plasma over the surface of the wafer while the wafer is in the load lock;

transferring the wafer from the load lock into the plasma enhanced chemical vapor deposition chamber; and

forming an etch stop layer over the surface of the wafer.

20. The method of claim 19, wherein flowing the remote plasma over the polished surface of the wafer comprises reducing a metal oxide on the metal portion of the polished surface.