METHODS, MEMORY CONTROLLERS AND DEVICES FOR WEAR LEVELING A MEMORY

• US 20100318719A1
• Filed: 06/12/2009
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Keays, Brady L., Wong, Wanmo
• Application Number:
  US12/483,712
• Publication Number:
  US 20100318719A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

The present disclosure includes methods, memory controllers and devices for wear leveling a memory. One method embodiment includes selecting, in at least a substantially random manner, a number of memory locations as at least a portion of a sample subset, the sample subset including fewer than all memory locations of the memory. A memory location having a particular wear level characteristic is identified from among the sample subset of memory locations, and data is written to the memory location identified from among the sample subset.

Claims

1. A method for wear leveling a memory, the method comprising:

selecting, in at least a substantially random manner, a number of memory locations of the memory as at least a portion of a sample subset, the sample subset including fewer than all of the memory locations of the memory;

identifying from among the sample subset of memory locations, a memory location having a particular wear level characteristic; and

writing data to the memory location identified from among the sample subset.

2. The method of claim 1, wherein the method includes identifying from among the sample subset of memory locations, a memory location having a cycle count below a particular threshold.

3. The method of claim 1, wherein the method includes identifying from among the sample subset of memory locations, a memory location having a lowestmost cycle count.

4. The method of claim 3, wherein the method includes selecting, as at least a portion of the sample set, an initial memory location by an ordered selection process.

5. The method of claim 4, wherein the initial memory location of the ordered selection process is a least significant memory location of the memory.

6. The method of claim 4, wherein the initial memory location of the ordered selection process is a most significant memory location of the memory.

7. The method of claim 4, wherein the initial memory location of the ordered selection process is a last memory location accessed before an initiating event.

8. The method of claim 4, wherein the initial memory location of the ordered selection process has a lowestmost cycle count of all the memory locations of the memory at an initiating event.

9. The method of claim 8, wherein the initiating event is an idle period of the memory.

10. The method of claim 8, wherein the initiating event is power-up of the memory.

11. The method of claim 8, wherein the initiating event is expiration of a time duration.

12. The method of claim 8, wherein the initiating event is occurrence of a particular cycle count.

13. The method of claim 8, wherein the initiating event is initiating of a certain wear leveling routine.

14. The method of claim 4, wherein the method includes:

selecting as at least a portion of a subsequent sample subset of memory locations, a memory location located at an offset from the initial memory location selected by the ordered process of a prior sample subset;

selecting, at least in a substantially random manner, a number of memory locations as at least another portion of the subsequent sample subset, the subsequent sample subset including fewer than all of the memory locations of the memory;

identifying from among the subsequent sample subset of memory locations, a memory location having the particular wear level characteristic; and

writing data to the memory location identified from among the subsequent sample subset.

15. The method of claim 14, wherein the offset is one memory location.

16. The method of claim 15, wherein the offset is negative.

17. The method of claim 15, wherein the offset is incremented in a round robin manner so as to eventually include each one of all memory locations in a sample subset.

18. The method of claim 14 wherein each of the respective memory locations are a logical block address.

19. The method of claim 14, wherein each of the respective memory locations are a physical block address.

20. The method of claim 1, wherein data from an originating memory location is moved to the memory location identified from among the sample subset.

21. A method for wear leveling a memory, the method comprising:

selecting, in at least a substantially random manner, a number of memory locations of the memory as a random sample subset, the random sample subset including fewer than all of the memory locations of the memory;

selecting, by an ordered selection process, a number of memory locations of the memory as an ordered sample subset;

identifying from among the random sample subset and the ordered sample subset, a memory location having a lowestmost cycle count; and

writing data to the memory location identified from among the sample subset.

22. A method for wear leveling a memory, the method comprising:

determining, at power-up of the memory, cycle counts of all blocks on the memory;

including, in a first wear leveling operation after power-up, a block having the lowest cycle count of all blocks in a sample subset of blocks;

selecting, in at least a substantially random manner, an additional number of blocks into the sample subset, the additional number of blocks being substantially fewer than all blocks;

identifying from among the sample subset, a destination block having a lowestmost cycle count; and

writing data to the identified destination block.

23. The method of claim 22, wherein the data written to the identified destination block is moved from a block to be wear leveled.

24. The method of claim 22, wherein the method includes including, in the sample subset of blocks for wear leveling operations subsequent to the first wear leveling operation after power-up, a block selected by an ordered routine that will eventually include each block in a sample subset.

25. The method of claim 24, wherein the selection routine first selects a block having the lowestmost cycle count of all blocks at an initiating event.

26. The method of claim 24, wherein the routine selects a block having a logical block address adjacent the logical block address of a previously included block not selected in a substantially random manner into the sample subset.

27. The method of claim 26, wherein the routine selects each block at least once for inclusion in a respective sample subset.

28. The method of claim 27, wherein the routine includes selecting respective blocks in a round robin order.

29. The method of claim 22, wherein the method includes providing a statistically small percentage of all blocks in each sample subset.

30. The method of claim 22, wherein the method includes providing less than one percent of all blocks in each sample subset.

31. The method of claim 30, wherein the method includes providing approximately 0.25 percent of all blocks in each sample subset.

32. The method of claim 22, wherein the method includes providing a number of blocks that yield wear leveling performance within a given range of performance level with respect to a wear leveling performance expected where the destination block has a lowest absolute cycle count.

33. The method of claim 22, wherein each act of selecting, in at least a substantially random manner, is accomplished at least in part using a pseudo-random number generator.

34. The method of claim 33, wherein the method includes implementing the pseudo-random number generator in firmware.

35. The method of claim 33, wherein the method includes seeding the pseudo-random number generator using a value stored in the memory at an initiating event.

36. The method of claim 33, wherein the method includes implementing the pseudo-random number generator to provide a low correlation between selected blocks of a particular sample subset.

37. The method of claim 33, wherein the method includes implementing the pseudo-random number generator to provide a low correlation between selected blocks of different sample subsets.

38. The method of claim 33, wherein the method include selecting the block to be wear leveled by a static wear leveling process.

39. The method of claim 33, wherein the method includes selecting the block to be wear leveled by a dynamic wear leveling process.

40. A method for wear leveling a memory, the method comprising:

selecting a subset of all logical blocks, the subset including;

at least one logical block determined from an ordered selection process, the ordered selection process configured to select each logical block once before the ordered selection process selects any logical block for a second time, and

at least one logical block determined from at least a substantially random selection process;

determining from the subset of logical blocks, a corresponding subset of physical blocks;

identifying a lowest cycle count from among the subset of physical blocks; and

writing data to the identified physical block.

41. The method of claim 40, further comprising reading the data from an originating physical block and wherein writing data comprises writing the read data to the identified physical block.

42. The method of claim 40, wherein further comprising receiving the data from a host and wherein writing data comprises writing the received data to the identified physical block.

43. A memory device, comprising:

a memory having a number of memory locations; and

control circuitry coupled to the memory and configured to;

determine, from among a representative sample of the memory locations, a destination memory location having a lowestmost cycle count; and

write data to the destination memory location.

44. The memory device of claim 43, wherein the control circuitry is further configured to at least pseudo-randomly select a portion of the memory locations included in the representative sample.

45. The memory device of claim 44, wherein the control circuitry is further configured to include in the representative sample a memory location having an absolute lowestmost cycle count from among the number of memory locations at memory power-on.

46. The memory device of claim 43, wherein the control circuitry is further configured to include in the representative sample one memory location selected from among the number of memory locations by a round robin process, wherein the round robin process begins with the memory location having an absolute lowestmost cycle count from among the number of memory locations at memory power-on.

47. The memory device of claim 43, wherein the control circuitry is further configured to identify, in response to a wear leveling analysis, an originating memory location having the data to write.

48. The method of claim 43, wherein the control circuitry is further configured to determine and write in response to receiving the data from a host.

49. A memory device, comprising:

a number of FLASH memory arrays; and

control circuitry coupled to the FLASH memory arrays and configured to;

at least substantially randomly select a sample subset of fewer than all logical blocks associated with the FLASH memory arrays;

determine physical blocks corresponding to the logical blocks of the sample subset;

identify, from the determined physical blocks, a physical block having a lowestmost cycle count of the determined physical blocks; and

write data to the physical block identified as having have the lowestmost cycle count of the determined physical blocks.

50. The memory device of claim 49, wherein the control circuitry is further configured to move data from an originating physical block to the physical block determined to have the lowestmost cycle count of the determined physical blocks.

51. The memory device of claim 49, wherein the control circuitry is further configured to receive data from a host and write the read data to the physical block determined to have the lowestmost cycle count of the determined physical blocks.

52. The memory device of claim 49, wherein the control circuitry is further configured to select, as a portion of the sample set, a logical block corresponding to a physical block having a lowestmost cycle count at an initiating event.

53. The memory device of claim 52, wherein the initiating event is an idle period of the memory device.

54. The memory device of claim 52, wherein the initiating event is power-up of the memory device.

55. The memory device of claim 49, wherein the control circuitry is further configured to select as a portion of at least some sample subsets a logical block corresponding to a physical block located at a non-zero offset from a physical block having the lowestmost cycle count at an initiating event.

56. The memory device of claim 55, wherein the offset is different for each respective selection of a sample subset.

57. The memory device of claim 56, wherein the offset changes linearly by a fixed increment for each respective selection of a sample subset.

58. A memory controller, comprising:

a pseudo-random number generator; and

control circuitry in communication with the pseudo-random number generator and configured to;

select a number of logical blocks of a FLASH memory based on output of the pseudo-random number generator;

determine physical blocks corresponding to the selected logical blocks;

identify which of the determined physical blocks has a lowestmost cycle count of the determined physical blocks; and

write data to the physical block identified as having the lowestmost cycle count of the determined physical blocks in response to a wear leveling operation;

wherein for a first selection of logical blocks the lowestmost cycle count is an absolute lowestmost cycle count of all physical blocks of the FLASH memory, and wherein, for a selection of logical blocks subsequent to the first selection of logical blocks, the lowestmost cycle count can be larger than the absolute lowestmost cycle count.

59. The memory device controller of claim 58, wherein the control circuitry is configured to select at least one physical block by a non-random process, wherein for the first selection, the physical block having the lowestmost cycle count of all the physical blocks at power-up of the FLASH memory is selected.

60. The memory device controller of claim 59, wherein the non-random process is a linear process selecting physical blocks in a round-robin manner.