PROCESSOR INSTRUCTION GRADUATION TIMEOUT

• US 20100318774A1
• Filed: 06/12/2009
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Abandoned Application

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Abts, Dennis C., Godfrey, Aaron F.
• Application Number:
  US12/483,902
• Publication Number:
  US 20100318774A1
• Time in Patent Office: Days
• US Class Current: 712/234
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

Claims

1. A method of resetting a hung processor, comprising:

setting a graduation timeout counter after a first program instruction graduates;

resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires; and

resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

2. The method of resetting a hung processor of claim 1, wherein the graduation timeout counter is set using a timeout value specified in a register.

3. The method of resetting a hung processor of claim 2, wherein resetting the graduation timeout counter comprises resetting the graduation timeout counter to the timeout value specified in the register.

4. The method of resetting a hung processor of claim 1, wherein resetting the processor comprises clearing any remaining in-flight instructions from the processor'"'"'s pipeline.

5. The method of resetting a hung processor of claim 1, further comprising approximately identifying the instruction that hung in the processor.

6. The method of resetting a hung processor of claim 5, wherein resetting the processor further comprises restarting execution in error mode at the instruction identified as approximately the instruction that hung the processor.

7. The method of resetting a hung processor of claim 1, wherein resetting the processor comprises leaving intact the architectural state of the processor not altered between a fence instruction graduated prior to the instruction that hung in the processor and the first fence instruction subsequent to the instruction that hung in the processor.

8. A computer processor comprising a graduation timeout error handler operable to:

set a graduation timeout counter after a first program instruction graduates;

reset the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires; and

reset the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

9. The computer processor of claim 8, wherein the graduation timeout counter is set using a timeout value specified in a register.

10. The computer processor of claim 9, wherein resetting the graduation timeout counter comprises resetting the graduation timeout counter to the timeout value specified in the register.

11. The computer processor of claim 8, wherein resetting the processor comprises clearing any remaining in-flight instructions from the processor'"'"'s pipeline.

12. The computer processor of claim 8, the error handler further operable to approximately identify the instruction that hung in the processor.

13. The computer processor of claim 12, wherein resetting the processor further comprises restarting execution in error mode at the instruction identified as approximately the instruction that hung the processor.

14. The computer processor of claim 8, wherein resetting the processor comprises leaving intact the architectural state of the processor not altered between a fence instruction graduated prior to the instruction that hung in the processor and the first fence instruction subsequent to the instruction that hung in the processor.

15. A multiprocessor computer system, comprising a plurality of processors distributed across a plurality of node coupled by a processor interconnect network, one or more of the processors operable to:

set a graduation timeout counter after a first program instruction graduates;

reset the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires; and

reset the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

16. The multiprocessor computer system of claim 15, wherein a failed message in the processor interconnect network results in the graduation timeout counter expiring before requested data is received in the processor.

17. The multiprocessor computer system of claim 15, wherein resetting the processor comprises clearing any remaining in-flight instructions from the processor'"'"'s pipeline.

18. The multiprocessor computer system of claim 15, the one or more of the processors further operable to approximately identify the instruction that hung in the processor.

19. The multiprocessor computer system of claim 18, wherein resetting the processor further comprises restarting execution in error mode at the instruction identified as approximately the instruction that hung the processor.

20. The multiprocessor computer system of claim 15, wherein resetting the processor comprises leaving intact the architectural state of the processor not altered between a fence instruction graduated prior to the instruction that hung in the processor and the first fence instruction subsequent to the instruction that hung in the processor.