SCALABLE, DYNAMIC POWER MANAGEMENT SCHEME FOR SWITCHING ARCHITECTURES UTILIZING MULTIPLE BANKS

• US 20100318821A1
• Filed: 10/22/2009
• Published: 12/16/2010
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kwan, Bruce, Matthews, Brad, Agarwal, Puneet
• Granted Patent: US 8,385,148 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

According to one general aspect, a method may include receiving data from a network device. In some embodiments, the method may include writing the data to a memory bank that is part of a plurality of at least single-ported memory banks that have been grouped to act as a single at least dual-ported aggregated memory element. In various embodiments, the method may include monitoring the usage of the plurality of memory banks. In one embodiment, the method may include, based upon a predefined set of criteria, placing a memory bank that meets the predefined criteria in a low-power mode.

Claims

1. A method comprising:

receiving data from a network device;

writing the data to a memory bank that is part of a plurality of at least single-ported memory banks that have been grouped to act as a single at least dual-ported aggregated memory element;

monitoring the usage of the plurality of memory banks; and

based upon a predefined set of criteria, placing a memory bank that meets the predefined criteria in a low-power mode.

2. The method of claim 1, wherein writing includes:

selecting a memory bank to write the data to;

determining if the selected memory bank is currently in a low-power mode;

if the selected memory bank is currently in a low-power mode, restoring the selected bank to a normal operating mode; and

writing the data to the selected memory bank.

3. The method of claim 1, wherein writing includes:

selecting a memory bank to write the data to, such that a maximum possible number of memory banks may be in a low-power mode.

4. The method of claim 1, wherein the predefined set of criteria include:

a predefined number of non-full memory banks that must be kept in a normal operating mode.

5. The method of claim 1, wherein writing includes:

writing data to a memory bank that includes the most amount of data but is not full.

6. The method of claim 1, wherein monitoring includes:

detecting the completion of a write operation;

determining if the write operation caused a memory bank to become full;

if so, determining if at least one other memory bank is operating in a normal operating mode and is not full; and

if not, removing a memory bank from a low-power mode and placing the memory bank into a normal operating mode.

7. The method of claim 1, wherein monitoring includes:

reducing the power consumption of the aggregated memory element as the usage of the plurality of memory banks is reduced.

8. The method of claim 1, further including:

based upon the predefined set of criteria, placing a memory bank that is a low-power mode in a normal operating mode.

9. The method of claim 1, wherein placing a memory bank in a low-power mode includes:

placing the memory bank in either a first low-power mode or a second low-power mode;

wherein the first low-power mode includes maintaining the integrity of any data stored within the memory bank; and

wherein the second low-power mode includes reducing the power consumption of the memory bank below that required to maintain the integrity of any data stored within the memory bank.

10. An apparatus comprising:

a plurality of ingress ports configured to receive data from at least one other apparatus;

an aggregated memory element configured to store at least part of the data received from the at least one other apparatus,

wherein the aggregated memory element includes a plurality of at least single-ported memory banks arranged to substantially act as a single at least dual-ported aggregated memory element;

a memory controller configured to;

monitor the usage of the aggregated memory element, and

based upon a predefined set of criteria, place a memory bank that meets the predefined criteria in a low-power mode; and

a plurality of egress ports configured to transmit data to at least one other apparatus.

11. The apparatus of claim 10, wherein the memory controller is configured to:

select a memory bank to write the data to;

determine if the selected memory bank is currently in a low-power mode;

if the selected memory bank is currently in a low-power mode, restore the selected bank to a normal operating mode; and

cause the aggregated memory element to write the data to the selected memory bank.

12. The apparatus of claim 10, wherein the memory controller is configured to:

select a memory bank to write data to, such that a maximum possible number of memory banks may be in a low-power mode.

13. The apparatus of claim 10, wherein the predefined set of criteria include:

a predefined number of non-full memory banks that must be kept in a normal operating mode.

14. The apparatus of claim 10, wherein aggregated memory element is configured to:

write data to a memory bank that includes the most amount of data but is not full.

15. The apparatus of claim 10, wherein the memory controller is configured to:

detect the completion of a write operation;

determine if the write operation caused a memory bank to become full;

if so, determine if at least one other memory bank is operating in a normal operating mode and is not full; and

if not, remove a memory bank from a low-power mode and placing the memory bank into a normal operating mode.

16. The apparatus of claim 10, wherein the memory controller is configured to:

reduce the power consumption of the aggregated memory element as the usage of the plurality of memory banks is reduced.

17. The apparatus of claim 10, wherein the memory controller is configured to:

based upon the predefined set of criteria, place a memory bank that is a low-power mode in a normal operating mode.

18. The apparatus of claim 10, wherein the memory controller is configured to:

place the memory bank in either a first low-power mode or a second low-power mode;

wherein the first low-power mode includes maintaining the integrity of any data stored within the memory bank; and

wherein the second low-power mode includes reducing the power consumption of the memory bank below that required to maintain the integrity of any data stored within the memory bank.

19. A computer program product for storing information, the computer program product being tangibly embodied on a computer-readable medium and including executable code that, when executed, is configured to cause a networking apparatus to:

receive data from a network device;

write the data to a memory bank that is part of a plurality of at least single-ported memory banks that have been grouped to act as a single at least dual-ported aggregated memory element;

monitor the usage of the plurality of memory banks; and

based upon a predefined set of criteria, control whether or not members of the plurality of memory banks are placed in a low-power mode.

20. The computer program product of claim 19, wherein the executable code, when executed, is configured to cause the networking apparatus to:

utilize a largest-bank-not-full placement policy to restrict storage of data to a subset to the plurality of memory banks.