NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20100320526A1
• Filed: 03/19/2010
• Published: 12/23/2010
• Est. Priority Date: 06/22/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJIWARA, Tomoko, MIKAJIRI, Yoshimasa, KITO, Masaru, KIDOH, Masaru, KATSUMATA, Ryota, TANAKA, Hiroyasu, FUKUZUMI, Yoshiaki, AOCHI, Hideaki, MATSUNAMI, Junya, ISHIDUKI, Megumi, OOTA, Shigeto, KIRISAWA, Ryouhei, KOMORI, Yosuke
• Application Number:
  US12/727,730
• Publication Number:
  US 20100320526A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a memory unit; and

a circuit unit provided between the semiconductor substrate and the memory unit,

the memory unit including;

a stacked structural unit having a plurality of electrode films alternately stacked with a plurality of inter-electrode-film insulating films in a first direction perpendicular to a major surface of the substrate;

a first semiconductor pillar piercing the stacked structural unit in the first direction; and

a first storage unit provided corresponding to an intersection between the electrode films and the first semiconductor pillar,

the circuit unit including;

a first transistor having a first source region of a first conductivity type and a first drain region of the first conductivity type;

a second transistor having a second source region of a second conductivity type and a second drain region of the second conductivity type;

a first interconnect including silicide provided on a side of the first transistor and the second transistor opposite to the semiconductor substrate;

a first contact plug made of polysilicon of the first conductivity type electrically connecting the first interconnect to at least one selected from the first source region and the first drain region; and

a second contact plug made of polysilicon of the second conductivity type electrically connecting the first interconnect to at least one selected from the second source region and the second drain region.

2. The device according to claim 1, wherein the silicide contained in the first interconnect includes at least one selected from WSi₂ and TiSi₂.

3. The device according to claim 1, wherein the circuit unit further includes

a second interconnect made of metal provided above the first interconnect, and

a conductive unit connecting the first interconnect and the second interconnect, the conductive unit being made of a material having a reactivity with silicon lower than a reactivity of the second interconnect with silicon.

4. The device according to claim 3, wherein an electrical resistance of the second interconnect is lower than an electrical resistance of the first interconnect.

5. The device according to claim 3, wherein the first interconnect includes tungsten silicide and the second interconnect includes tungsten.

6. The device according to claim 3, wherein

the second interconnect includes tungsten, and

the conductive unit includes at least one selected from Ti and TiN.

7. The device according to claim 3, wherein the circuit unit further includes a conductive layer provided to cover at least a portion of a face of the second interconnect on the semiconductor substrate side, the conductive layer being made of a material having a reactivity with silicon lower than the reactivity of the second interconnect with silicon.

8. The device according to claim 1, wherein:

the first transistor further includes a first channel region provided between the first source region and the first drain region, a first gate insulating film provided on the first channel region, and a first gate electrode provided on the first gate insulating film; and

the second transistor further includes a second channel region provided between the second source region and the second drain region, a second gate insulating film provided on the second channel region, and a second gate electrode provided on the second gate insulating film.

9. The device according to claim 1, wherein the first transistor and the second transistor are divided by an STI (Shallow Trench Insulator).

10. The device according to claim 1, wherein the electrode films include at least one selected from amorphous silicon including an impurity and polysilicon including an impurity.

11. The device according to claim 1, wherein the inter-electrode-films insulating film include silicon oxide.

12. The device according to claim 1, wherein the first storage unit includes a charge storage layer provided between the electrode films and a side face of the first semiconductor pillar.

13. The device according to claim 12, further comprising:

a first outer side insulating film provided between the first storage unit and each of the electrode films; and

a first inner side insulating film provided between the first storage unit and the first semiconductor pillar.

14. The device according to claim 1, wherein the memory unit further includes:

a second semiconductor pillar piercing the stacked structural unit in the first direction;

a second storage unit provided corresponding to an intersection between the electrode films and the second semiconductor pillar; and

a connection portion electrically connecting the first semiconductor pillar and the second semiconductor pillar.

15. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

forming a first transistor and a second transistor on a major surface of a semiconductor substrate, the first transistor including a first source region of a first conductivity type and a first drain region of the first conductivity type, the second transistor including a second source region of a second conductivity type and a second drain region of the second conductivity type;

forming a first contact plug, a second contact plug, and a first interconnect layer, the first contact plug being made of polysilicon of the first conductivity type and aligned in a first direction perpendicular to the major surface to connect to at least one selected from the first source region and the first drain region, the second contact plug being made of polysilicon of the second conductivity type and aligned in the first direction to connect to at least one selected from the second source region and the second drain region, the first interconnect layer including silicide and being connected to one selected from the first contact plug and the second contact plug; and

forming a memory unit above the first interconnect layer, the memory unit including;

a stacked structural unit having a plurality of electrode films alternately stacked with a plurality of inter-electrode-film insulating films in the first direction;

a first semiconductor pillar piercing the stacked structural unit in the first direction; and

a first storage unit provided corresponding to an intersection between the electrode films and the first semiconductor pillar.

16. The method according to claim 15, wherein the silicide contained in the first interconnect layer includes at least one selected from WSi₂ and TiSi₂.

17. The method according to claim 15, comprising:

forming, between the first interconnect layer and the stacked structural unit, a conductive unit electrically connected to the first interconnect layer; and

further forming, above the first interconnect layer and between the first interconnect layer and the stacked structural unit, a second interconnect layer made of metal having a reactivity with silicon higher than a reactivity of the conductive unit with silicon, the second interconnect layer being electrically connected to the conductive unit.

18. The method according to claim 17, wherein

the second interconnect layer includes tungsten, and

the conductive unit includes at least one selected from Ti and TiN.

19. The method according to claim 17, wherein the forming of the second interconnect layer includes:

making a trench and forming a conductive layer on an inner side of the trench, the trench communicating with the conductive unit, the conductive layer being made of a material having a reactivity with silicon lower than the reactivity of the second interconnect layer with silicon; and

filling a metal forming the second interconnect layer into a remaining space of the trench.

20. The method according to claim 19, wherein

the conductive layer includes at least one selected from Ti and TiN, and

the metal forming the second interconnect layer includes tungsten.