Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices

• US 20100320534A1
• Filed: 08/27/2010
• Published: 12/23/2010
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Rexer, Christopher Lawrence, Pan, James
• Granted Patent: US 8,669,623 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Claims

1-20. -20. (canceled)

21. A method of forming a semiconductor structure which includes a shielded gate FET, the method comprising:

forming a plurality of trenches in a semiconductor region using a mask which includes;

(i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer;

forming a shield dielectric layer extending along at least lower sidewalls of each trench;

forming a thick bottom dielectric (TBD) along a bottom of each trench, the first oxidation barrier layer preventing formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD;

forming a shield electrode disposed in a bottom portion of each trench; and

forming a gate electrode over the shield electrode in each trench.

22. The method of claim 21 wherein the semiconductor region comprises silicon, and the thick bottom dielectric is formed by oxidizing the silicon using a local oxidation of silicon (LOCOS) process.

23. The method of claim 21 wherein at least a portion of the second insulating layer remains over and protects the first oxidation barrier layer following formation of the plurality of trenches.

24. The method of claim 21 wherein the semiconductor region includes a drift region extending over a substrate, the drift region having a lower doping concentration than the substrate, wherein the plurality of trenches are formed to extend through the drift region and terminate within the substrate.

25. The method of claim 21 further comprising:

prior to forming the gate electrode, forming an inter-electrode dielectric (IED) layer over the shield electrode.

26. The method of claim 25 wherein the step of forming the IED layer comprises:

depositing an oxide layer; and

recessing the oxide layer into each trench, the first oxidation barrier layer protecting the surface of the semiconductor region during recessing the oxide layer.

27. The method of claim 26 wherein the oxide layer is recessed into each trench using dry etch only.

28. The method of claim 21 further comprising:

forming a gate dielectric lining upper sidewalls of each trench.

29. The method of claim 28 wherein the gate dielectric is thinner than the shield dielectric layer.

30. The method of claim 21 further comprising:

forming a second oxidation barrier layer extending along opposing sidewalls of each trench but being discontinuous along the bottom of each trench, the second oxidation barrier layer preventing formation of a dielectric layer along the opposing sidewalls of each trench during formation of the TBD.

31. The method of claim 30 wherein the first and the second insulating layers comprise oxide.

32. The method of claim 31 wherein the first and the second oxidation barrier layers comprise nitride.

33. The method of claim 21 further comprising:

after forming the plurality of trenches, rounding bottom corners of each trench.

34. The method of claim 33 wherein the semiconductor region comprises silicon, and the bottom corners of each trench are rounded using a silicon etch process, wherein the second insulating layer protects the first oxidation barrier layer during the silicon etch process.

35. The method of claim 21 wherein the shielded gate FET is formed in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the method further comprising:

in the one or more FET regions;

forming a body region in the semiconductor region; and

forming source regions in the body region adjacent each trench.

36. The method of claim 35 further comprising:

forming an interconnect layer in the one or more FET regions and in the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.

37. A method of forming a semiconductor structure which includes a shielded gate FET, the method comprising:

forming a plurality of trenches in a semiconductor region using a mask which includes;

(i) a first oxide layer over a surface of the semiconductor region, (ii) a first nitride layer over the first oxide layer, and (iii) a second oxide layer over the first nitride layer;

forming a shield oxide layer extending along sidewalls and bottom of each trench;

forming nitride spacers along opposing sidewalls of each trench over the shield oxide layer;

oxidizing silicon to form a thick bottom oxide (TBO) along the bottom of each trench, the first nitride layer preventing formation of oxide along the surface of the semiconductor region during the oxidizing of silicon, and the nitride spacers preventing formation of oxide along the opposing sidewalls of each trench during the oxidizing of silicon;

forming a shield electrode in a bottom portion of each trench over the TBO;

forming an inter-electrode dielectric (IED) layer extending over the shield electrode in each trench; and

forming a gate electrode in each trench over the IED layer.

38. The method of claim 37 wherein at least a portion of the second oxide layer remains over and protects the first nitride layer following formation of the plurality of trenches.

39. The method of claim 37 wherein the semiconductor region includes a drift region extending over a substrate, the drift region having a lower doping concentration than the substrate, wherein the plurality of trenches is formed to extend through the drift region and terminate within the substrate.

40. The method of claim 37 wherein the step of forming the IED layer comprises:

depositing a third oxide layer; and

recessing the third oxide layer into each trench, the first oxidation barrier layer protecting the surface of the semiconductor region during recessing the third oxide layer.

41. The method of claim 40 wherein the third oxide layer is recessed into each trench using dry etch only.

42. The method of claim 37 further comprising:

forming a gate oxide lining upper sidewalls of each trench.

43. The method of claim 42 wherein the gate oxide is thinner than the shield oxide layer.

44. The method of claim 37 further comprising:

after forming the plurality of trenches, rounding bottom corners of each trench.

45. The method of claim 44 wherein the semiconductor region comprises silicon, and the bottom corners of each trench are rounded using a silicon etch process, wherein the second oxide layer protects the first nitride layer during the silicon etch process.

46. The method of claim 37 wherein the shielded gate FET is formed in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the method further comprising:

in the one or more FET regions;

forming a body region in the semiconductor region; and

forming source regions in the body region adjacent each trench.

47. The method of claim 46 further comprising:

forming an interconnect layer in the one or more FET regions and in the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.

48. The method of claim 46 wherein the shield electrode in each trench is biased to same potential as the source regions.

49. The method of claim 46 wherein the one or more FET regions include a drain region over which the body region extends, the drain and source regions are of opposite conductivity type to the body region, and the shield electrode in each trench is biased to same potential as the drain region.

50. The method of claim 37 wherein the shield electrode in each trench is biased to same potential as the gate electrode.

51. A semiconductor structure which includes a shielded gate FET, comprising:

a plurality of trenches in a semiconductor region;

a shield electrode in a bottom portion of each trench;

a gate electrode over the shield electrode;

a shield dielectric lining lower sidewalls of each trench; and

a thick bottom dielectric (TBD) lining a bottom of each trench, wherein a thickness of the TBD is different than a thickness of the shield dielectric.

52. The structure of claim 51 wherein the thickness of the TBD is greater than the thickness of the shield dielectric.

53. The structure of claim 51 further comprising:

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode; and

a gate dielectric lining upper sidewalls of each trench on each side of the gate electrode.

54. The structure of claim 53 wherein a thickness of the gate dielectric is less than the thickness of the shield dielectric.

55. The structure of claim 51 wherein the shielded gate FET is in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the structure further comprising:

in the one or more FET regions;

a body region in the semiconductor region; and

source regions in the body region adjacent each trench.

56. The structure of claim 55 further comprising:

an interconnect layer extending over the one or more FET regions and over the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.