Method for Forming MEMS Devices Having Low Contact Resistance and Devices Obtained Thereof

• US 20100320606A1
• Filed: 06/17/2010
• Published: 12/23/2010
• Est. Priority Date: 06/18/2009
• Status: Active Grant

• Current Assignee: IMEC International, Katholieke Universiteit Leuven
• Original Assignee: IMEC International, Katholieke Universiteit Leuven
• Inventors: Jain, Ajay, Claes, Gert, Heck, John, Severi, Simone
• Granted Patent: US 8,487,386 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Abstract

The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Claims

1. A MEMS device comprising a silicon-germanium (SiGe) layer formed over a dielectric stack which is formed over a an another layer, the dielectric layer stack comprising an opening exposing the conductive layer, whereby an interface layer separates the SiGe layer from the dielectric layer stack at least in the opening and from the exposed another layer in the opening.

2. The MEMS device according to claim 1, wherein the another layer is a metal conductive layer.

3. The MEMS device according to claim 2, wherein the MEMS device is placed over a supporting substrate comprising an interconnect pattern and the metal conductive layer is the top metal layer of the interconnect pattern.

4. The MEMS device according to claim 1, wherein the another layer is a second SiGe layer.

5. The MEMS device according to claim 1, wherein the interface layer comprises a layer of TiN in contact with the SiGe layer.

6. The MEMS device according to claim 5, wherein the interface layer further comprises a layer of Ti in contact with the TiN layer and the another layer.

7. The MEMS device according to claim 1, wherein the interface layer comprises a layer of TaN in contact with the SiGe layer.

8. The MEMS device according to claim 7, wherein the interface layer further comprises a layer of Ta in contact with the TaN layer and the another layer.

9. The MEMS device according to claim 1, wherein the SiGe layer is also formed within the opening.

10. A method for manufacturing a MEMS device comprising:

forming an opening in a dielectric stack to expose at least a portion of an another layer below the dielectric stack;

forming an interface layer at least on the sidewalls of the opening and on the exposed surface of the another layer, and

forming a silicon-germanium (SiGe) layer at least in a portion of the opening,

whereby the interface layer separates the SiGe layer from the dielectric layer stack at least in the opening and from the exposed another layer.

11. The method according to claim 10, wherein the another layer is a conductive metal layer.

12. The method according to claim 11, wherein the metal layer is the top metal layer of an interconnect pattern of a CMOS substrate.

13. The method according to claim 10, wherein the another layer is a second SiGe layer.

14. The method according to claim 10, wherein the interface layer comprises a layer of TiN in contact with the SiGe layer.

15. The method according to claim 14, wherein the interface layer further comprises a layer of Ti in contact with the TiN layer and the another layer.

16. The method according to claim 10, wherein the interface layer comprises a layer of TaN in contact with the SiGe layer.

17. The method according to claim 16, wherein the interface layer further comprises a layer of Ta in contact with the TaN layer and the another layer.

18. The method according to claim 10, wherein a soft sputter etch step is performed after the opening is formed and before forming of the interface layer.

19. The method according to claim 10, wherein the SiGe layer fills at least a portion of the opening.

20. The method according to claim 10, wherein the SiGe layer is deposited on the interface layer without having the interface layer exposed to an oxidizing ambient.