Transistor, electronic device including a transistor and methods of manufacturing the same

• US 20100321279A1
• Filed: 12/04/2009
• Published: 12/23/2010
• Est. Priority Date: 06/17/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-yoon, Son, Kyoung-seok, Jung, Ji-sim, Kwon, Jang-yeon, Lee, Kwang-hee
• Application Number:
  US12/591,914
• Publication Number:
  US 20100321279A1
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

Disclosed are a transistor, an electronic device and methods of manufacturing the same, the transistor including a photo relaxation layer between a channel layer and a gate insulating layer in order to suppress characteristic variations of the transistor due to light. The photo relaxation layer may be a layer of a material capable of suppressing variations in a threshold voltage of the transistor due to light. The photo relaxation layer may contain a metal oxide such as aluminum (Al) oxide. The channel layer may contain an oxide semiconductor.

Claims

1. A transistor, comprising:

a source and a drain;

a channel layer on the source and drain, the channel layer including an oxide semiconductor;

a photo relaxation layer on the channel layer, wherein the photo relaxation layer includes aluminum (Al) oxide;

a gate insulating layer on the photo relaxation layer, wherein the photo relaxation layer is between the channel layer and the gate insulating layer in order to suppress characteristic variations of the transistor due to light; and

a gate on the gate insulating layer.

2. The transistor of claim 1, wherein the photo relaxation layer consists of a material capable of suppressing variations in a threshold voltage of the transistor due to the light.

3. The transistor of claim 1, wherein the aluminum (Al) oxide is Al₂O₃.

4. The transistor of claim 1, wherein the photo relaxation layer has a thickness of about 1-nm to about 50-nm.

5. The transistor of claim 1, wherein the oxide semiconductor is a zinc oxide (ZnO)-based oxide.

6. The transistor of claim 5, wherein the ZnO-based oxide is HfInZnO.

7. The transistor of claim 1, wherein the gate insulating layer includes silicon (Si) nitride.

8. The transistor of claim 1, wherein the gate insulating layer includes Si oxide.

9. The transistor of claim 1, wherein the gate insulating layer has a thickness of about 50-nm to about 400-nm.

10. The transistor of claim 1, wherein the transistor is a top-gate thin film transistor.

11. The transistor of claim 1, wherein the transistor is a bottom-gate thin film transistor.

12. The transistor of claim 11, further comprising an etch stop layer on the channel layer,

wherein the source and the drain are on the etch stop layer and separately contact separate ends of the channel layer.

13. The transistor of claim 1, further comprising an etch stop layer on the channel layer, wherein the source and the drain are on the etch stop layer and separately contact separate ends of the channel layer.

14. A flat panel display device, comprising the transistor of claim 1.

15. The flat panel display device of claim 14, wherein the flat panel display device is one selected from the group consisting of a liquid crystal display (LCD) device and an organic light emitting display (OLED) device.

16. The flat panel display device of claim 14, wherein the transistor is configured as a switching device or a driving device.

17. The flat panel display device of claim 14, wherein the photo relaxation layer includes a material capable of suppressing variations in a threshold voltage of the transistor due to the light.

18. The flat panel display device of claim 14, wherein the aluminum (Al) oxide is Al₂O₃.