Electrostatic Discharge Structures and Methods of Manufacture

• US 20100321842A1
• Filed: 06/23/2009
• Published: 12/23/2010
• Est. Priority Date: 06/23/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: VOLDMAN, Steven H., GEBRESELASIE, Ephrem G.
• Granted Patent: US 8,054,597 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

Claims

1. A structure comprising an electrostatic discharge (ESD) network and electrically connected in series to a through wafer via.

2. The structure of claim 1, wherein the through wafer via is electrically connected directly to VSS.

3. The structure of claim 2, wherein the VSS is one of ground and a substrate rail.

4. The structure of claim 1, wherein the ESD network is located under a bond pad.

5. The structure of claim 1, wherein the ESD network includes an inductor positioned under a bond pad.

6. The structure of claim 5, wherein the inductor is an inductive coil that has a resistance of less than about 10 ohms and is structured to carry a current of about 1 amp to about 10 amps.

7. The structure of claim 6, wherein the ESD network is electrically connected to a power rail.

8. The structure of claim 5, wherein the ESD network includes at least one of a diode and MOSFET.

9. The structure of claim 5, further comprising a plurality of through wafer via structures surrounding the ESD network.

10. The structure of claim 5, further comprising a conductor shield to insulate a surrounding area from injection current.

11. An ESD circuit comprising:

a bond pad;

an ESD network located under the bond pad; and

a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

12. The ESD circuit of claim 11, wherein the ESD network includes an ESD element and an inductive coil.

13. The ESD circuit of claim 12, wherein the inductive coil is one of copper and aluminum located under the bond pad and electrically connected in series directly to the through wafer via structure.

14. The ESD circuit of claim 12, wherein the inductive coil has a resistance of less than about 10 ohms and is structured to carry a current of about 1 amp to about 10 amps.

15. The ESD circuit of claim 12, further comprising a conductor shield located under the bond pad to insulate a surrounding area from injection current generated from the inductive coil.

16. The ESD circuit of claim 12, further comprising a plurality of through wafer via structures surrounding the ESD network.

17. The ESD circuit of claim 12, wherein the inductive coil is about 2 microns wide to about 8 microns wide and about 0.5 microns thick to about 4 microns thick.

18. The ESD circuit of claim 12, wherein the ESD network includes an ESD element and an inductive coil electrically connected in series by an input node.

19. A method of manufacturing an ESD network, comprising:

forming a bond pad above an interlevel dielectric layer;

forming an ESD element having an inductive coil under the bond pad, in the interlevel dielectric layer; and

forming a through via structure by lithographic, etching and deposition processes, and which is electrically connected to the inductive coil.

20. The method of claim 19, wherein the inductive coil is formed by depositing a thin film of conductive material in the interlevel dielectric layer.