PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY

• US 20100322000A1
• Filed: 06/18/2010
• Published: 12/23/2010
• Est. Priority Date: 06/19/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jaehun, Shim, Sunil, Hur, Sunghoi, Kim, Hansoo, Kim, Kihyun
• Granted Patent: US 8,514,625 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

Claims

1. A method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate comprising:

first programming a memory cell to be programmed to one among a first set of states;

first programming at least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states; and

following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

2. The method of claim 1 wherein the set of states comprises a set of discrete charge levels that correspond to a set of threshold voltages for the memory cells at a time when the memory cells are sensed during a read operation.

3. The method of claim 1 wherein the at least one neighboring memory cell neighbors the memory cell to be programmed in one of:

a first horizontal direction, a second horizontal direction; and

the vertical direction.

4. The method of claim 3 wherein the at least one neighboring memory cell neighbors the memory cell to be programmed in a diagonal direction that extends in one of:

both the first horizontal and vertical directions;

both the second horizontal and vertical directions; and

both the first horizontal and second horizontal directions.

5. The method of claim 1 wherein first programming the at least one neighboring memory cell comprises performing first programming a plurality of neighboring memory cells that neighbor the memory cell to be programmed.

6. The method of claim 1 wherein the at least one neighboring memory cell neighbors the memory cell to be programmed in the horizontal direction.

7. The method of claim 1 wherein the at least one neighboring memory cell neighbors the memory cell to be programmed in the vertical direction

8. The method of claim 1 wherein the at least one neighboring memory cell neighbors the memory cell to be programmed in a diagonal direction.

9. The method of claim 1 wherein the first and second sets of states each comprise a range of defined threshold voltage levels that correspond to a predetermined data value.

10. The method of claim 9 wherein the second set of states is four states, corresponding to two-bit data values and wherein the first programming programs one of the least-significant-bit of the data value and the most-significant bit of the data value and wherein the second programming programs the other of the least-significant-bit of the data value and the most-significant bit of the data value.

11. The method of claim 1:

wherein memory cells neighboring each other in the vertical direction are connected in series in a cell string along a vertical channel;

wherein cell strings neighboring each other in a first horizontal direction are connected to a common bit line;

wherein cell strings neighboring each other in a second horizontal direction are connected to a common string select line; and

wherein gates of cells positioned on a same horizontal plane are connected to a common word line.

12. The method of claim 11 wherein:

the first programming of the memory cell to be programmed is performed on a memory cell of a cell string connected to a first string select line and connected to a first word line;

the first programming of the at least one neighboring memory cell that neighbors the memory cell to be programmed is performed on a memory cell of a cell string connected to the first string select line and connected to a second word line that neighbors the first word line,

and wherein second programming the memory cell to be programmed to one among a second set of states is performed on the memory cell of the cell string connected to the first string select line and connected to the first word line.

13. The method of claim 12 wherein the multiple-bit programming method proceeds in a minimum-to-maximum word line direction for memory cells connected to each of the string select lines.

14. The method of claim 12 wherein the multiple-bit programming method proceeds in a minimum-to-maximum word line direction for memory cells connected to a first set of the string select lines, and proceeds in a maximum-to-minimum word line direction for memory cells connected to a second set of the string select lines, wherein the first set and second set of string select lines are alternating.

15. The method of claim 11 wherein:

the first programming of the memory cell to be programmed is performed on a memory cell of a cell string connected to a first string select line;

the first programming of the at least one neighboring memory cell that neighbors the memory cell to be programmed is performed on a memory cell of a cell string connected to a second string select line that neighbors the first string select line, and further comprising;

first programming a second neighboring memory cell that neighbors the at least one neighboring memory cell to be programmed to one among the first set of states, the second neighboring memory cell connected to a third string select line that neighbors the second string select line opposite the first string select line;

and wherein second programming the memory cell to be programmed to one among a second set of states follows the first programming of the second neighboring memory cell.

16. The method of claim 11 wherein:

the first programming of the memory cell to be programmed is performed on a memory cell of a cell string connected to a first string select line;

the first programming of the at least one neighboring memory cell that neighbors the memory cell to be programmed is performed on a memory cell of a cell string connected to a second string select line that neighbors the first string select line, and further comprising;

first programming a second neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states, the second neighboring memory cell connected to the first string select line;

and wherein second programming the memory cell to be programmed to one among a second set of states follows the first programming of the second neighboring memory cell.

17. The method of claim 11:

wherein first sets of cell strings comprise memory cells that are activated in response to a first set of word lines and wherein second sets of cell strings comprise memory cells that are activated in response to a second set of word lines, wherein the cell strings of the first sets of cell strings and cell strings of the second sets of cell strings alternate in horizontal position in the second horizontal direction, and

wherein the cell to be programmed is associated with a cell string of the first set of cell strings and wherein the at least one neighboring memory cell is associated with a cell string of the second set of cell strings.

18. The method of claim 11 further comprising partitioning cell strings connected to the same bit line into first and second blocks and wherein first and second programming of memory cells of the first block are completed prior to first and second programming of memory cells of the second block.

19. The method of claim 11 further comprising partitioning memory cells of cell strings connected to neighboring word lines into first and second blocks and wherein first and second programming of memory cells of the first block are completed prior to first and second programming of memory cells of the second block.