NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME

• US 20100322006A1
• Filed: 06/22/2009
• Published: 12/23/2010
• Est. Priority Date: 06/22/2009
• Status: Abandoned Application

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Van Buskirk, Michael, Kwan, Ming Sang, Fang, Shenqing, Suh, Youseok
• Application Number:
  US12/489,226
• Publication Number:
  US 20100322006A1
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines.

Claims

1. A memory cell string, comprising:

a first select gate of said memory cell string comprising a first plurality of elements;

a plurality of wordlines coupled to said first select gate; and

a second select gate comprising a second plurality of elements coupled to said plurality of wordlines wherein the distances between one element of said first and said second plurality of elements and said plurality of wordlines are the same as the distances that exist between each wordline of said plurality of wordlines.

2. The memory cell string string of claim 1 wherein said plurality of wordlines comprise a first wordline a last wordline and a plurality of internal wordlines.

3. The memory cell string of claim 1 wherein an element of said first plurality of elements is the same size as said plurality of wordlines.

4. The memory cell string of claim 1 wherein said first plurality of elements comprises two elements of different sizes.

5. The memory cell string of claim 1 wherein said first plurality of elements comprises two elements of equal sizes.

6. The memory cell string of claim 1 wherein said first plurality of elements comprises three elements of the same size.

7. The memory cell string of claim 2 wherein during an erase operation, said one element of said first and second plurality of elements is biased with an erase voltage such that said first and said last wordline have the same bias as does said internal wordline.

8. A NAND flash memory device, comprising:

a memory controller; and

a NAND memory cell string, comprising;

a first select gate of a NAND memory cell string that comprises a first plurality of elements;

a plurality of wordlines coupled to said first select gate wherein said plurality of wordlines are separated by the same distance; and

a second select gate of a NAND memory cell string comprising a second plurality of elements coupled to said plurality of wordlines wherein the distances between a neighboring element of said first and said second plurality of elements and said plurality of wordlines are the same as the distance between each wordline of said plurality of wordlines.

9. The flash memory device of claim 8 wherein said plurality of wordlines comprise a first wordline a last wordline and a plurality of internal wordlines.

10. The flash memory device of claim 8 wherein an element of said first plurality of elements is the same size as said plurality of wordlines.

11. The flash memory device of claim 8 wherein said first plurality of elements comprises two elements of different sizes.

12. The flash memory device of claim 8 wherein said first plurality of elements comprises two elements of equal sizes.

13. The flash memory device of claim 8 wherein said first plurality of elements comprises three elements of the same size.

14. The flash memory device of claim 9 wherein during an erase operation, said one element of said first and second plurality of elements is biased with an erase voltage such that said first and said last wordline have the same bias as does said internal wordline.

15. A process for forming a memory cell string, comprising:

forming a first select gate of a wordline string comprising a first plurality of elements;

forming a plurality of wordlines to be coupled to said first select gate; and

forming a second select gate comprising a second plurality of elements to be coupled to said plurality of wordlines wherein the distances formed between a first element of said first and said second plurality of elements and said first and last wordlines respectively are the same as the distance that is formed between each wordline of said plurality of wordlines.

16. The process of claim 15 wherein said plurality of wordlines comprise a first wordline a last wordline and a plurality of internal wordlines.

17. The process of claim 15 wherein an element of said first plurality of elements is the same size as said plurality of wordlines.

18. The process of claim 15 wherein said first plurality of elements comprises two elements of different sizes.

19. The process of claim 15 wherein said first plurality of elements comprises two elements of equal sizes.

20. The process of claim 16 wherein during an erase operation, said one element of said first and second plurality of elements is biased with an erase voltage such that said first and said last wordline have the same bias as does said internal wordline.