NON-VOLATILE MEMORY PROGRAMMABLE THROUGH AREAL CAPACITIVE COUPLING

• US 20100322010A1
• Filed: 08/26/2010
• Published: 12/23/2010
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Liu, David K.Y.
• Granted Patent: US 7,920,426 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A two terminal programmable non-volatile device situated on a substrate comprising:

a floating gate comprised of polysilicon;

a first n-type diffusion region coupled to a first terminal; and

a second n-type diffusion region coupled to a second terminal; and

wherein the second n-type diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and a voltage applied to such second n-type diffusion region;

an n-type channel coupling said first n-type diffusion region and second n-type diffusion region;

wherein said n-type channel is adapted to have a low resistance when the device is in an unprogrammed state, and a high resistance when the device is in a programmed state;

further wherein the device can be placed into a programmed state using a programming voltage applied to said first terminal of said first n-type diffusion region and second terminal of said second n-type diffusion region such that charge can be imparted to said floating gate through areal capacitive coupling.

2. The programmable device of claim 1 wherein said coupling ratio is at least 90%.

3. The programmable device of claim 1 wherein said floating gate can be erased.

4. The programmable device of claim 3 wherein said device can be re-programmed.

5. The programmable device of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said second n-type diffusion.

7. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

8. The programmable device of claim 7 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

9. The programmable device of claim 1, further including a second programmable device coupled in a paired latch arrangement such that a datum and its complement are stored in said paired latch.

10. The programmable device of claim 1, wherein said threshold voltage of said device can be set to multiple discrete levels.

11. The programmable device of claim 1, wherein the device is part of a programmable memory array.

6. The programmable device of claim 6, wherein said read signal is less than about 1 volt.

12. A one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices and programmed through two terminals, characterized in that:

a. said OTP memory device has a floating gate overlying at least in part an n-type channel situated in an n-type diffusion region;

wherein said n-type channel is adapted to have a low resistance when the device is in an unprogrammed state, and a high resistance when the device is in a programmed state; and

b. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices, including said n-type diffusion region which is used by said devices;

c. the OTP memory device can be set to said programmed state by areal capacitive coupling to said floating gate through a voltage applied to the two terminals, including a source terminal and a drain terminal.

13. The OTP memory device of claim 12 wherein said coupling ratio is at least 90%.

14. The OTP memory device of claim 12 wherein said floating gate can be erased.

15. The OTP memory device of claim 14 wherein said device can be re-programmed.

16. The OTP memory device of claim 14 wherein said floating gate is eraseable by an erase voltage applied to said source region.

17. The OTP memory device of claim 12 wherein a state of said floating gate can be determined by a read signal applied to said drain.

18. The OTP memory device of claim 12 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

19. The OTP memory device of claim 12, further including a second OTP memory device coupled in a paired latch arrangement such that a datum and its complement are stored in said paired latch.

20. The OTP memory device of claim 12, wherein a threshold voltage of said device can be set to multiple discrete levels.