TERNARY AND HIGHER MULTI-VALUE DIGITAL SCRAMBLERS/DESCRAMBLERS

• US 20100322414A1
• Filed: 08/26/2010
• Published: 12/23/2010
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,864,079 B1
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.

Claims

1. A method of descrambling a sequence of p scrambled n-state symbols with n>

2 and p>

1 into a sequence of p descrambled n-state symbols, an n-state symbol being able to assume one of n states, comprising;

inputting a first scrambled n-state symbol of the sequence of p scrambled n-state symbols on a first input of a descrambling n-state function;

inputting a second n-state symbol on a second input of the descrambling n-state function;

generating by a processor of a descrambled n-state symbol in accordance with the descrambling n-state function, wherein a truth table representing the descrambling n-state function is implemented in a memory that is accessed by the processor;

wherein a relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is defined by the n-state truth table that is commutative and self reversing and that satisfies the following equations for all possible states of A and B;

A sc B=C;

 

 

(1)

C sc B=A; and

 

 

(2)

A sc C=B; and

 

 

(3)

repeating the previous steps until all symbols of the sequence of p scrambled n-state symbols have been descrambled by the processor.

2. The method of claim 1, further comprising:

generating the second n-state symbol on an output of an n-state Linear Feedback Shift Register.

3. The method of claim 1, wherein a lowest of n states is a first state and the descrambled n-state symbol does not have the first state when first scrambled n-state symbol and the second n-state symbol have a same state.

4. The method of claim 1, wherein the sequence of p scrambled n-state symbols has been created by scrambling a sequence of p n-state symbols by a scrambling method that applies the descrambling n-state logic function.

5. The method of claim 1, wherein n is an odd integer.

6. The method of claim 1, wherein the processor is part of a communication system.

7. An apparatus for descrambling a plurality of scrambled n-state symbols including a first scrambled n-state symbol, each n-state symbol enabled to assume one of n states with n>

2, comprising;

a descrambling device having a first and a second input and an output, the first input enabled to receive a signal representing the first scrambled n-state symbol, the second input enabled to receive a signal representing a second n-state symbol and the output providing a signal representing a descrambled n-state symbol;

wherein a relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is determined by a commutative self reversing n-state logic function sc, that satisfies the following equations for all possible states of A and B;

A sc B=C;

 

 

(1)

C sc B=A; and

 

 

(2)

A sc C=B; and

 

 

(3)

wherein the descrambling device includes a memory that implements a truth table that defines the commutative self reversing n-state logic function sc.

8. The apparatus as claimed in claim 7, further comprising:

an n-state Linear Feedback Shift Register (LFSR) including an output that provides the signal representing the second n-state symbol.

9. The apparatus as claimed in claim 7, wherein the first scrambled n-state symbol and the second n-state symbol are represented by a first and a second plurality of binary signals.

10. The apparatus as claimed in claim 7, wherein the commutative self reversing n-state logic function is realized by implementing its truth table in a memory.

11. The apparatus as claimed in claim 7, further comprising a corresponding scrambling apparatus, including:

a scrambling device, having a first input enabled to receive a signal representing a first n-state symbol, a second input enabled to receive a signal representing the second symbol, and an output enabled to provide the first scrambled n-state symbol;

wherein the scrambling device implements the commutative self reversing n-state logic function sc.

12. The apparatus of claim 11, wherein the corresponding scrambler has an identical structure as the descrambler.

13. The apparatus of claim 7, wherein the descrambler is part of a communication system.

14. The apparatus of claim 7, wherein a signal representing the first scrambled n-state symbol is part of a spread spectrum signal.

15. A method for scrambling a sequence of p n-state symbols with p>

1, including a first n-state symbol, each n-state symbol enabled to assume one of n states with n>

2, each n-state symbol being represented by a signal, comprising;

inputting the first n-state symbol of the sequence of p n-state symbols on a first input of a scrambling n-state function;

inputting a second n-state symbol on a second input of the scrambling n-state function;

generating by a processor of a scrambled n-state symbol in accordance with the scrambling n-state function, wherein a truth table representing the scrambling n-state function is implemented in a memory that is accessed by the processor;

wherein a relationship between the first n-state symbol which may be called A, the second n-state symbol which may be called B and the scrambled n-state symbol which may be called C is defined by the n-state truth table that is commutative and self reversing and that satisfies the following equations for all possible states of A and B;

A sc B=C;

 

 

(1)

C sc B=A; and

 

 

(2)

A sc C=B; and

 

 

(3)

repeating the previous steps until all symbols of the sequence of p n-state symbols have been scrambled by the processor.

16. The method of claim 15, further comprising:

inputting the scrambled n-state symbol on an input of an n-state Linear Feedback Shift Register.

17. The method of claim 15, wherein a lowest of n states is a first state and the scrambled n-state symbol does not have the first state when first scrambled n-state symbol and the second n-state symbol have a same state.

18. The method of claim 15, wherein the processor is part of a communication system.

19. The method of claim 15, wherein a signal representing the scrambled n-state symbol is part of a spread spectrum signal.