MICROPROCESSOR WITH IMPROVED THERMAL MONITORING AND PROTECTION MECHANISM

• US 20100324750A1
• Filed: 09/01/2010
• Published: 12/23/2010
• Est. Priority Date: 10/03/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Gaskins, Darius D., Holthaus, Charles John
• Granted Patent: US 8,412,962 B2
• Time in Patent Office: Days
• US Class Current: 700/299
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature.

Claims

1. A microprocessor, comprising:

a temperature sensor, configured to monitor a temperature of core logic of the microprocessor during operation thereof;

operating point information, from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature, each of the N operating points having a different combination of operating frequency and voltage, wherein the N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate said highest and lowest operating points; and

a control circuit, coupled to said temperature sensor, configured to transition operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by said temperature sensor within a temperature range whose upper bound is said first temperature.

2. The microprocessor as recited in claim 1, further comprising:

clock generation circuitry, coupled to said control circuit, configured to generate a clock signal for provision to the core logic, wherein the core logic is configured to operate to execute program instructions according to said clock signal;

wherein said control circuit is configured to control said clock generation circuitry to generate said clock signal to transition operation of the core logic among the N operating points without stopping operation of the core logic.

3. The microprocessor as recited in claim 1, wherein the N combinations of operating frequency and voltage include at least six different voltages.

4. The microprocessor as recited in claim 3, wherein the N combinations of operating frequency and voltage include at least four different frequencies.

5. The microprocessor as recited in claim 1, wherein the N operating points comprise at least ten operating points.

6. The microprocessor as recited in claim 1, further comprising:

an input, coupled to said control circuit, configured to receive information specifying said temperature range from system software.

7. The microprocessor as recited in claim 6, wherein said temperature range information comprises information specifying a lower bound of the temperature range.

8. The microprocessor as recited in claim 1, wherein an amount of power dissipated by the core logic while operating at each of the N operating points is monotonically increasing.

9. The microprocessor as recited in claim 1,

wherein said highest operating point comprises a first voltage at which the microprocessor may reliably operate at a first frequency and at said first temperature;

and

wherein said operating point information further comprises;

a second voltage at which the microprocessor may reliably operate at said first frequency and at a second temperature, wherein the second temperature is less than the first temperature and the second voltage is less than the first voltage;

wherein the control circuit is further configured to cause the microprocessor to operate at the first frequency and at the second voltage rather than the first voltage when the operating temperature drops below the second temperature while operating at the first frequency and at the first voltage.

10. The microprocessor as recited in claim 1,

wherein said first temperature is the maximum temperature at which the microprocessor will reliably operate at said highest operating point, wherein said highest operating point comprises a first frequency and a first voltage, wherein said first frequency is the maximum frequency at which the microprocessor will reliably operate at said first temperature and said first voltage;

wherein said operating point information further comprises;

a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage;

wherein said second frequency is greater than said first frequency;

wherein said second temperature is less than said first temperature;

wherein said control circuit is further configured to cause the microprocessor to operate at said second voltage and said second frequency rather than said first voltage and said first frequency, in response to detecting that while operating at said first voltage and said first frequency the operating temperature dropped to said second temperature.

11. The microprocessor as recited in claim 10,

wherein said operating point information further comprises:

a third voltage at which the microprocessor may reliably operate at said second frequency and at a third temperature, wherein the third temperature is less than the second temperature and the third voltage is less than the second voltage;

wherein the control circuit is further configured to cause the microprocessor to operate at the second frequency and at the third voltage rather than the second voltage when the operating temperature drops below the third temperature while operating at the second frequency and at the second voltage.

12. A method for dynamically operating a microprocessor core at a performance-optimum frequency within a temperature range bounded by an upper and lower temperature, the method comprising:

determining N operating points at which the microprocessor core may reliably operate at the upper temperature, each of the N operating points having a different combination of operating frequency and voltage, wherein the N operating points comprise a highest operating point, a lowest operating point, and a plurality of intermediate operating points, wherein the microprocessor comprises the N operating points;

monitoring a temperature of the microprocessor core during operation thereof, wherein the microprocessor comprises a temperature sensor that performs said monitoring; and

transitioning operation of the microprocessor core among the N operating points to attempt to keep the operating temperature of the microprocessor core within the temperature range, in response to said monitoring, wherein the microprocessor comprises control logic coupled to the temperature sensor, wherein the control logic performs said transitioning.

13. The method as recited in claim 12, wherein said transitioning among the N operating points is performed without stopping operation of the microprocessor core.

14. The method as recited in claim 12, further comprising:

programming the temperature range into the microprocessor, prior to said transitioning.

15. The method as recited in claim 12,

wherein said highest operating point comprises a first voltage at which the microprocessor may reliably operate at a first frequency and at said upper temperature;

and

wherein said operating point information further comprises;

a second voltage at which the microprocessor may reliably operate at said first frequency and at a second temperature, wherein the second temperature is less than the upper temperature and the second voltage is less than the first voltage;

wherein the method further comprises;

causing the microprocessor to operate at the first frequency and at the second voltage rather than the first voltage when the operating temperature drops below the second temperature while operating at the first frequency and at the first voltage.

16. The method as recited in claim 12,

wherein said upper temperature is the maximum temperature at which the microprocessor will reliably operate at said highest operating point, wherein said highest operating point comprises a first frequency and a first voltage, wherein said first frequency is the maximum frequency at which the microprocessor will reliably operate at said upper temperature and said first voltage;

wherein said operating point information further comprises;

a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage;

wherein said second frequency is greater than said first frequency;

wherein said second temperature is less than said upper temperature;

wherein the method further comprises;

causing the microprocessor to operate at said second voltage and said second frequency rather than said first voltage and said first frequency, in response to detecting that while operating at said first voltage and said first frequency the operating temperature dropped to said second temperature.

17. The method as recited in claim 16,

wherein said operating point information further comprises:

a third voltage at which the microprocessor may reliably operate at said second frequency and at a third temperature, wherein the third temperature is less than the second temperature and the third voltage is less than the second voltage;

wherein the method further comprises;

causing the microprocessor to operate at the second frequency and at the third voltage rather than the second voltage when the operating temperature drops below the third temperature while operating at the second frequency and at the second voltage.

18. A computer program product for use with a computing device, the computer program product comprising:

a computer usable storage medium, having computer readable program code embodied in said medium, for providing a microprocessor, said computer readable program code comprising;

first program code for providing a temperature sensor, configured to monitor a temperature of core logic of the microprocessor during operation thereof;

second program code for providing operating point information, from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature, each of the N operating points having a different combination of operating frequency and voltage, wherein the N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate said highest and lowest operating points; and

third program code for providing a control circuit, coupled to said temperature sensor, configured to transition operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by said temperature sensor within a temperature range whose upper bound is said first temperature.

19. The computer program product as recited in claim 18, said computer readable program code further comprising:

fourth program code for providing clock generation circuitry, coupled to said control circuit, configured to generate a clock signal for provision to the core logic, wherein the core logic is configured to operate to execute program instructions according to said clock signal;

wherein said control circuit is configured control said clock generation circuitry to generate said clock signal to transition operation of the core logic among the N operating points without stopping operation of the core logic.