MEMORY-DAUGHTER-CARD-TESTING METHOD AND APPARATUS

• US 20100324854A1
• Filed: 08/27/2010
• Published: 12/23/2010
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Grossmeier, Alan M., Steinberger, Michael L., Resnick, David R., Bethard, Roger A., Snyder, Van L., Schwoerer, Gerald A., Marquardt, Kelly J.
• Granted Patent: US 8,126,674 B2
• Time in Patent Office: Days
• US Class Current: 702/108
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card'"'"'s functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card'"'"'s functions.

Claims

1. An apparatus comprising:

a first memory card that includes;

a plurality of memory chips;

a high-speed external card interface connected to write and read data to and from the memory chips; and

a test engine configured to control the high-speed interface and the memory chips in order to provide testing functions to a second substantially identical memory card.

2. The apparatus of claim 1, wherein the first memory card further comprises:

a plurality of memory controllers, each one of the plurality of memory controllers connected to control a subset of the plurality of the memory chips on the first memory card.

3. The apparatus of claim 2, wherein the first memory card further comprises:

a plurality of caches, each one of the plurality of caches operatively coupled to a corresponding one of the plurality of memory controllers on the first memory card.

4. The apparatus of claim 1, wherein the first memory card further comprises:

a control interface, the control interface configured to program the test engine and to initialize, control, and observe test sequences.

5. The apparatus of claim 1, further comprising a test system operably coupled to the first memory card and configured to cause the test engine in the first memory card to test a second memory card, the test system comprising:

a test fixture having a first interface connectable to the first memory card and a second interface connectable to the second memory card, such that at least some inputs from the first interface are connected to corresponding outputs of the second interface, and at least some outputs from the first interface are connected to corresponding inputs of the second interface; and

a test controller operable to send configuration data through the first interface and into the first memory card to cause a testing function to be performed under the control of the first memory card when suitable first and second memory cards are connected to the test fixture.

6. The apparatus of claim 1, wherein the test engine includes a microcode sequencer and a result test checker.

7. The apparatus of claim 1, wherein the high-speed external card interface includes a plurality of serializer-deserializer (SerDes) ports.

8. A method comprising:

providing a first memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the first memory card writes and reads data to and from the plurality of memory chips of the first memory card;

providing a second memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the second memory card writes and reads data to and from the plurality of memory chips of the second memory card, and wherein the second memory card is substantially identical to the first memory card;

connecting the high-speed external card interface of the first memory card to the high-speed external card interface of the substantially identical second memory card; and

testing the second memory card by writing and reading data through the high-speed interface of the first memory card and the high-speed interface of the second memory card to and from the plurality of memory chips on the second memory card under control of the first memory card.

9. The method of claim 8, wherein the first memory card includes a plurality of memory controllers, the method further comprising:

controlling a subset of the plurality of memory chips of the first memory card using the plurality of memory controllers of the first memory card.

10. The method of claim 9, wherein the first memory card includes a plurality of caches, the method further comprising:

connecting each one of the plurality of caches of the first memory card to a corresponding one of the plurality of memory controllers of the first memory card.

11. The method of claim 8, further comprising:

programming the first memory card to perform the testing of the second memory card, and

initializing, controlling, and observing test sequences in the first card corresponding to the testing of the second memory card.

12. The method of claim 8, further comprising

providing a test fixture having a first interface and a second interface;

connecting the first interface of the test fixture to the first memory card and connecting the second interface of the test fixture to the second memory card such that at least some inputs from the first interface of the test fixture are connected to corresponding outputs of the second interface, and at least some outputs from the first interface of the test fixture are connected to corresponding inputs of the second interface of the test fixture; and

sending configuration data through the first interface of the test fixture and into the first memory card to cause a testing function to be performed under control of the first memory card when suitable first and second memory cards are connected to the test fixture.

13. The method of claim 8, wherein the configuring of the high-speed external card interface of the first memory card includes loading microcode into the first memory card.

14. The method of claim 10, wherein the high-speed external card interface of the first memory card includes a plurality of serializer-deserializer (SerDes) ports, the method further comprising:

connecting each one of the plurality of SerDes ports of the first memory card to at least one of the plurality of caches of the first memory card.

15. An apparatus comprising:

a first memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the first memory card writes and reads data to and from the plurality of memory chips of the first memory card;

a second memory card that has a plurality of memory chips and a high-speed external card interface, wherein the high-speed external card interface of the second memory card writes and reads data to and from the plurality of memory chips of the second memory card, and wherein the second memory card is substantially identical to the first memory card;

means for connecting the high-speed external card interface of the first memory card to the high-speed external card interface of the substantially identical second memory card; and

means for testing the second memory card by writing and reading data through the high-speed interface of the first memory card and the high-speed interface of the second memory card to and from the plurality of memory chips on the second memory card under control of the first memory card.

16. The apparatus of claim 15, the apparatus further comprising:

means for controlling a subset of the plurality of memory chips of the first memory card.

17. The apparatus of claim 15, wherein the high-speed external card interface of the first memory card includes a plurality of serializer-deserializer (SerDes) ports, wherein the first memory card includes a plurality of caches, the apparatus further comprising:

means for connecting each one of the plurality of SerDes ports of the first memory card to each one of the plurality of caches of the first memory card.

18. The apparatus of claim 15, wherein the means for testing includes:

means for programming the first memory card to perform the testing of the second memory card, and

means for initializing, controlling, and observing test sequences.

19. The apparatus of claim 15, further comprising

a test fixture having a first interface and a second interface;

means for connecting the first interface of the test fixture to the first memory card and means for connecting the second interface of the test fixture to the second memory card such that at least some inputs from the first interface of the test fixture are connected to corresponding outputs of the second interface, and at least some outputs from the first interface of the test fixture are connected to corresponding inputs of the second interface of the test fixture; and

means for sending configuration data through the first interface of the test fixture and into the first memory card to cause a testing function to be performed under control of the first memory card when suitable first and second memory cards are connected to the test fixture.

20. The apparatus of claim 15, further comprising means for loading microcode into the first memory card.