MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE USING SAME

• US 20100325342A1
• Filed: 07/16/2008
• Published: 12/23/2010
• Est. Priority Date: 07/20/2007
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Honda, Toshiyuki
• Application Number:
  US12/526,224
• Publication Number:
  US 20100325342A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

In a controller (memory controller) (2) that performs drive control of first and second flash memories (nonvolatile memories) (3a, 3b) in which multilevel memory cells are used in physical blocks, 64 page groups each including physical pages (9) provided in these physical blocks (8) are defined with respect to the plurality of physical blocks (8), and the physical pages (9) of the physical blocks (8) are grouped so that the boundaries of the page groups are defined behind the physical page (9) as the n-th page.

Claims

1. A memory controller for performing drive control with respect to a nonvolatile memory in which multilevel memory cells, each of which is configured to be capable of storing data of two or more bits, are used in physical blocks,

the memory controller comprising a main control part configured to be capable of interleaving and writing data in a plurality of the physical blocks,

wherein each of the plurality of physical blocks includes the multilevel memory cells, which are p in number, first to p-th multilevel memory cells (p is an integer of not less than 2),

in each of the p multilevel memory cells, n pages that are first to n-th pages are provided as physical pages that are writing units for data (n is an integer of not less than 2), wherein as compared with a time required for a data writing operation with respect to the first page, the time required for a data writing operation with respect to a subsequent page increases sequentially as the page number increases, and

in the case where in each of the plurality of physical blocks, page numbers are allocated sequentially to all the physical pages provided in the p multilevel memory cells in a predetermined order, the main control part defines, in the plurality of physical blocks, a plurality of page groups that include the physical pages provided in the physical blocks, and groups the physical pages of the plurality of physical blocks so that boundaries between the page groups are defined behind the physical pages as the n-th pages.

2. The memory controller according to claim 1, wherein the main control part groups the physical pages of the plurality of physical blocks so that each of the plurality of page groups includes the physical pages having the same page numbers in the plurality of physical blocks.

3. The memory controller according to claim 1, wherein in the case where data to be written in the nonvolatile memory are fed from outside, when transfer of data to be written is performed with respect to, among the plurality of physical pages included in the page groups, one physical page as the first page, the main control part performs transfer of data to be written with respect to another physical page of the same physical block included in the same page group as the page group including the above-mentioned physical page, and when transfer of data to be written is performed with respect to the physical page as the n-th page, the main control part performs transfer of data to be written with respect to a physical page of a physical block other than the physical block that includes the above-mentioned physical page as the n-th page.

4. A nonvolatile storage device comprising:

a nonvolatile memory in which multilevel memory cells each of which is configured to be capable of storing data of two or more bits are used in physical blocks; and

the memory controller according to claim 1.