Quiescent State Retention Mode for Processor

• US 20100325457A1
• Filed: 06/22/2009
• Published: 12/23/2010
• Est. Priority Date: 06/22/2009
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Berbessou, David, Lachwani, Manish
• Granted Patent: US 8,601,302 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.

Claims

1. A computer-implemented method of placing a processor into an quiescent state retention mode (QSRM), the method comprising:

under control of one or more computer systems configured with executable instructions,

freezing running user-space processes and kernel threads executing on the processor;

placing an input/output device coupled to the processor into a suspend mode;

configuring a wakeup source coupled to the processor to generate wakeup interrupts;

gating a clock defined in a clock gating register of the processor;

placing a linear regulator on a power management integrated circuit (PMIC) coupled to the processor into an off state;

placing a switching regulator on the PMIC into low power state;

preparing the PMIC to enter a low power mode;

setting a processor state retention mode in a clock control module coupled to the processor;

flushing a cache coupled to the processor;

disabling interrupt requests to the processor except for interrupts from the wakeup sources;

disabling processor scaling in the processor;

executing a wait for interrupt instruction configured to receive the wakeup interrupt from the wakeup source;

gating a main clock of the processor; and

placing the PMIC in the low power mode.

2. The method of claim 1, further comprising gating a serial peripheral interface clock and a universal serial bus clock after placing the switching regulator on the PMIC into low power state.

3. The method of claim 1, wherein the flushing comprises flushing a primary cache coupled to the processor and a secondary cache coupled to the processor.

4. The method of claim 1, further comprising placing external memory into self-refresh mode after preparing the PMIC to enter the low power mode.

5. The method of claim 1, wherein the placing of the input/output device into the suspend mode comprises saving input/output device state in a memory, putting the input/output device into a low power mode, and gating a clock driving the input/output device.

6. The method of claim 1, wherein the processor comprises an application processor able to gate clocks discretely.

7. The method of claim 1, wherein the wakeup sources comprise at least one of the following:

a PMIC event, a network interface, a realtime clock wakeup, or a power button.

8. The method of claim 1, wherein the disabling processor scaling comprises setting the processor to a maximum operational frequency supported by the processor.

9. The method of claim 1, further comprising gating or shutting down devices external to the processor.

10. A system of reducing power consumption in a portable electronic device, the system comprising:

a memory;

a processor coupled to the memory;

a kernel stored in the memory and configured to execute on the processor, the kernel being configured to maintain a switching regulator of a power management integrated circuit (PMIC) in a low power state after entering an quiescent state retention mode (QSRM).

11. The system of claim 10, further comprising a peripheral device coupled to the processor and wherein the kernel is configured to enter the QSRM by performing the following acts:

place the peripheral device into a low power state; and

configure a wakeup source in the peripheral device to generate a wakeup interrupt.

12. The system of claim 10, wherein the kernel is further configured to maintain memory in a self-refresh state after entering the QSRM.

13. The system of claim 10, wherein the switching regulator is configured to provide power to the processor.

14. The system of claim 10, wherein the kernel is further configured to execute a wait for interrupt (WFI) instruction.

15. The system of claim 10, wherein the kernel is configured to enter the QSRM by performing the following acts:

freeze a running user-space process and kernel thread executing on the processor;

configure a wakeup source to generate a wakeup interrupt;

gate a clock which is defined in a clock gating register coupled to the processor;

place into an off state a linear regulator of a PMIC which is configured to provide power to a gated device which is coupled to the processor;

place into low power state the switching regulator of a PMIC which is configured to provide power to the processor;

gate a serial peripheral interface clock or a universal serial bus clock or both which are coupled to the processor;

set a state retention mode for the processor in a clock control module which is coupled to the processor;

disable interrupt generation from a non-wakeup source;

disable processor scaling on the processor; and

gate a main clock of the processor.

16. The system of claim 15, wherein the kernel is further configured to place the PMIC into a low power mode after disabling processor scaling.

17. One or more computer-readable storage media storing instructions that, when executed by a processor, cause the processor to perform acts comprising:

freezing running processes and threads executing on a central processing unit (CPU);

placing input or output or both devices into a low power or suspend state;

configuring a wakeup source to generate a wakeup interrupt;

gating clocks defined in clock gating register;

placing into an off state a linear regulator configured to provide power to a gated device;

placing into low power state a switching regulator configured to provide power to the CPU;

gating a serial peripheral interface clock or a universal serial bus clock or both;

setting a state retention mode for the CPU in a clock control module;

disabling interrupts from a non-wakeup source; and

disabling CPU scaling.

18. The computer-readable storage media of claim 17, wherein the placing of input or output or both devices into a low power or suspend state comprises saving device state in a memory, putting the device into a low power mode, and gating clocks driving the device.

19. The computer-readable storage media of claim 17, further comprising placing a power management integrated circuit (PMIC) into a low power mode after gating the serial peripheral interface clock or the universal serial bus clock or both.

20. The computer-readable storage media of claim 17, wherein disabling processor scaling further comprises configuring the CPU to a maximum operational frequency supported by the CPU.

21. The computer-readable storage media of claim 17, further comprising flushing a CPU primary cache, or secondary cache, or both after setting the state retention mode in the clock control module.

22. The computer-readable storage media of claim 17, further comprising executing a wait for interrupt instruction after disabling CPU scaling.

23. The computer-readable storage media of claim 17, further comprising placing memory into a self-refresh mode.

24. The computer-readable storage media of method of claim 17, wherein the wakeup source comprises at least one of the following:

a power management event, a network interface, a realtime clock, or a power button.