Storage device, storage control device, data transfer intergrated circuit, and storage control method

• US 20100325522A1
• Filed: 08/27/2010
• Published: 12/23/2010
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ohyama, Sadayuki, Hanaoka, Yuji, Tsukamoto, Nina
• Granted Patent: US 8,448,047 B2
• Time in Patent Office: Days
• US Class Current: 714/770
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD

Abstract

A storage device is for restoring the data saved in a nonvolatile memory to a cache memory, even if there is not a read response from the nonvolatile memory. In a data saving operation, parity data of to-be-saved data is generated, and the to-be-saved data and the parity data having CRCs and AIDs added thereto are written into a flash memory. In a data restoring operation, if an operation to read data from the flash memory is not completed within a predetermined period of time, the data reading operation is suspended, and additional data is set. The to-be-saved data having a data error corrected with the parity data is then written into the cache memory.

Claims

1. A storage device comprising:

a data transfer unit that stores to-be-transferred data into a nonvolatile memory, when an abnormal end occurs, the to-be-transferred data including to-be-saved data stored in a cache memory and parity data for correcting a data error in the to-be-saved data, with an error detection code for detecting a data error being added to the to-be-saved data and the parity data;

a data reading unit that reads stripes from the nonvolatile memory when power is supplied to the storage device after an abnormal end, the stripes being formed by dividing the to-be-transferred data by a predetermined stripe size;

an additional data adding unit that adds additional data to a stripe until a size of the stripe becomes equal to the stripe size, when the data reading unit does not finish reading the stripe within a predetermined period of time;

a data error checking unit that determines whether a data error exists in the stripes, based on the error detection code added to the stripes read out by the data reading unit;

a data correcting unit that corrects a data error, using the stripes read out by the data reading unit, when the data error checking unit detects the data error; and

a data writing unit that writes into the cache memory to-be-saved data contained in stripes not having a data error detected by the data error checking unit, and writes into the cache memory to-be-saved data contained in stripes having a data error corrected by the data correcting unit.

2. The storage device according to claim 1, further comprising:

a first data saving unit that stores data of a predetermined size into the nonvolatile memory from a beginning address indicating a location of a beginning of storage of the to-be-saved data in the cache memory, when the storage device ends abnormally; and

a second data saving unit that stores data of a predetermined size into the nonvolatile memory from a final address indicating a location of an end of storage of the to-be-saved data in the cache memory, when the storage device ends abnormally.

3. The storage device according to claim 2, further comprising:

a saved data area calculating unit that, when the storage device ends abnormally, sets the beginning address of the to-be-saved data as a first start address that is a storage location of data to be first read from the cache memory by the first data saving unit, calculates a first reference value that is the smallest value of an integer N, with a value obtained by multiplying a predetermined boundary size by the integer N being larger than a value obtained by dividing the to-be-saved data by 2, sets a value obtained by multiplying the first reference value by the boundary size as a first data save size that is a size of data to be read from the cache memory by the first data saving unit, calculates a second reference value that is the smallest value of the integer N, with a value obtained by multiplying the boundary size by the integer N being larger than a value obtained by subtracting the first data save size from the size of the to-be-saved data, sets a value obtained by multiplying the second reference value by the boundary size as a second data save size that is a size of data to be read from the cache memory by the second data saving unit, and calculates a second start address that is a storage location of data to be first read from the cache memory by the second data saving unit, based on a final address of the to-be-saved data and the first data save size, wherein

the first data saving unit stores, into the nonvolatile memory, data of a size equivalent to the first data save size calculated by the saved data area calculating unit, the data being from the first start address calculated by the saved data area calculating unit in the to-be-saved data, and

the second data saving unit stores, into the nonvolatile memory, data of a size equivalent to the second data save size calculated by the saved data area calculating unit, the data being from the second start address calculated by the saved data area calculating unit in the to-be-saved data.

4. The storage device according to claim 1, wherein the data error checking unit determines whether a data error exists in the stripes, based on Cyclic Redundancy Checks (CRCs) added to the stripes.

5. The storage device according to claim 1, wherein the data error checking unit determines whether all the stripes exist, based on stripe identification numbers added to the stripes, the stripe identification numbers being for identifying the stripes.

6. A data transfer integrated circuit for storing to-be-transferred data into a nonvolatile memory, the to-be-transferred data including to-be-saved data stored in a cache memory and parity data for correcting a data error in the to-be-saved data, with an error detection code for detecting a data error being added to the to-be-saved data and the parity data,

the data transfer integrated circuit comprising:

a data reading unit that reads stripes from the nonvolatile memory, the stripes being formed by dividing the to-be-transferred data by a predetermined stripe size;

an additional data adding unit that adds additional data to a stripe until a size of the stripe becomes equal to the stripe size, when the data reading unit does not finish reading the stripe within a predetermined period of time;

a data error checking unit that determines whether a data error exists in the stripes, based on the error detection code added to the stripes read out by the data reading unit;

a data correcting unit that corrects a data error, using the stripes read out by the data reading unit, when the data error checking unit detects the data error; and

a data writing unit that writes into the cache memory to-be-saved data contained in stripes not having a data error detected by the data error checking unit, and writes into cache memory to-be-saved data contained in stripes having a data error corrected by the data correcting unit.

7. The data transfer integrated circuit according to claim 6, further comprising:

a first data saving unit that stores data of a predetermined size into the nonvolatile memory from a beginning address indicating a location of a beginning of storage of the to-be-saved data in the cache memory; and

a second data saving unit that stores data of a predetermined size into the nonvolatile memory from a final address indicating a location of an end of storage of the to-be-saved data in the cache memory.

8. A storage control method for controlling a storage device including a data transfer unit that stores to-be-transferred data into a nonvolatile memory when an abnormal end occurs, the to-be-transferred data including to-be-saved data stored in a cache memory and parity data for correcting a data error in the to-be-saved data, with an error detection code for detecting a data error being added to the to-be-saved data and the parity data,

the storage control method comprising:

reading stripes from the nonvolatile memory when power is supplied after an abnormal end, the stripes being formed by dividing the to-be-transferred data by a predetermined stripe size;

adding additional data to a stripe until a size of the stripe becomes equal to the stripe size, when the stripe is not read within a predetermined period of time at the reading;

determining whether a data error exists in the stripes, based on the error detection code added to the stripes read out at the reading;

correcting a data error, using the stripes read out at the reading, when the data error is determined at the determining; and

writing into the cache memory to-be-saved data contained in stripes not having a data error determined at the determining, and writing into the cache memory to-be-saved data contained in stripes having a data error corrected at the correcting.

9. The storage control method according to claim 8, further comprising:

storing data of a predetermined size into the nonvolatile memory from a beginning address indicating a location of a beginning of storage of the to-be-saved data in the cache memory, when an abnormal end occurs; and

storing data of a predetermined size into the nonvolatile memory from a final address indicating a location of an end of storage of the to-be-saved data in the cache memory, when an abnormal end occurs.

10. The storage control method according to claim 9, further comprising

setting, when an abnormal end occurs, the beginning address of the to-be-saved data as the first start address that is a storage location of data to be first read from the cache memory at the saving the data from the beginning address, calculating a first reference value that is the smallest value of an integer N, with a value obtained by multiplying a predetermined boundary size by the integer N being larger than a value obtained by dividing the to-be-saved data by 2, setting a value obtained by multiplying the first reference value by the boundary size as a first data save size that is a size of data to be read from the cache memory at the saving the data from the final address, calculating a second reference value that is the smallest value of the integer N, with a value obtained by multiplying the boundary size by the integer N being larger than a value obtained by subtracting the first data save size from the size of the to-be-saved data, setting a value obtained by multiplying the second reference value by the boundary size as a second data save size that is a size of data to be read from the cache memory at the saving the data from the final address, and calculating a second start address that is a storage location of data to be first read from the cache memory at the saving the data from the final address, based on a final address of the to-be-saved data and the first data save size,

the saving the data from the beginning address includes storing, into the nonvolatile memory, data of a size equivalent to the first data save size calculated at the calculating, the data being from the first start address calculated at the calculating in the to-be-saved data, and

the saving the data from the final address includes storing, into the nonvolatile memory, data of a size equivalent to the second data save size calculated at calculating, the data being from the second start address calculated by the calculating in the to-be-saved data.

11. The storage control method according to claim 8, wherein the determining includes determining whether a data error exists in the stripes, based on CRCs added to the stripes.

12. The storage control method according to claim 8, wherein the determining includes determining whether all the stripes exist, based on stripe identification numbers added to the stripes, the stripe identification numbers being for identifying the stripes.