SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
First Claim
1. A semiconductor device comprising:
- a drain region of a field-effect transistor disposed over a semiconductor substrate;
a channel forming region of the field-effect transistor disposed over the drain region;
a source region of the field-effect transistor disposed over the channel forming region;
a trench reaching the drain region from an upper surface of the source region;
a first insulating film disposed in the trench and disposed at a lower part of the trench;
a first conductive film disposed over the first insulating film in the trench and disposed at the lower part of the trench the first conductive film serving as a dummy gate electrode;
a gate insulating film of the field-effect transistor disposed over the first insulating film in the trench and disposed at a upper part of the trench; and
a gate electrode of the field-effect transistor disposed over the gate insulating film in the trench and disposed at the upper part of the trench,wherein the gate electrode and the first conductive film are separately disposed and are insulated from each other by an intervening second insulating film,wherein a thickness of the gate insulating film is less than a thickness of the first insulating film, andwherein an outer peripheral portion of the trench is filled with the first conductive film through the first insulating film such that a lead-out part of the first conductive film extends over the semiconductor substrate.
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Accused Products
Abstract
In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
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Citations
15 Claims
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1. A semiconductor device comprising:
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a drain region of a field-effect transistor disposed over a semiconductor substrate; a channel forming region of the field-effect transistor disposed over the drain region; a source region of the field-effect transistor disposed over the channel forming region; a trench reaching the drain region from an upper surface of the source region; a first insulating film disposed in the trench and disposed at a lower part of the trench; a first conductive film disposed over the first insulating film in the trench and disposed at the lower part of the trench the first conductive film serving as a dummy gate electrode; a gate insulating film of the field-effect transistor disposed over the first insulating film in the trench and disposed at a upper part of the trench; and a gate electrode of the field-effect transistor disposed over the gate insulating film in the trench and disposed at the upper part of the trench, wherein the gate electrode and the first conductive film are separately disposed and are insulated from each other by an intervening second insulating film, wherein a thickness of the gate insulating film is less than a thickness of the first insulating film, and wherein an outer peripheral portion of the trench is filled with the first conductive film through the first insulating film such that a lead-out part of the first conductive film extends over the semiconductor substrate. - View Dependent Claims (3, 4, 5, 6, 7, 14, 15)
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2. The semiconductor device according to claim 2, further comprising:
a protective diode including a conductive film formed over the semiconductor substrate and formed by same layer as the first conductive film. - View Dependent Claims (8, 9, 10, 11, 12, 13)
Specification