Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

• US 20100327419A1
• Filed: 06/26/2009
• Published: 12/30/2010
• Est. Priority Date: 06/26/2009
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gealer, Charles A., Muthukumar, Sriram
• Application Number:
  US12/459,226
• Publication Number:
  US 20100327419A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01065 : Terbium [Tb]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Claims

1. A package-on-package apparatus comprising:

a package substrate including a die side and a land side;

a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height; and

an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height.

2. The apparatus of claim 1, wherein the interposer has a ball-grid array, the apparatus further including:

a top package, wherein the top package includes at least one microelectronic device, and wherein the top package mates to the interposer ball-grid array.

3. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side; and

the top chip is a wire-bond chip disposed on the flip chip.

4. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a wire-bond second chip disposed above the flip chip; and

the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.

5. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a through-silicon via (TSV) second chip disposed on the flip chip; and

the top chip is a wire-bond subsequent chip disposed on the TSV second chip.

6. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a through-silicon via (TSV) second chip disposed on the flip chip;

a TSV third chip disposed on the TSV second chip; and

the top chip is a wire-bond fourth chip disposed on the TSV third chip.

7. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a through-silicon via (TSV) second chip disposed on the flip chip;

a TSV third chip disposed on the TSV second chip, wherein the TSV third chip is a plurality of TSV chips in a range from 2 to 8 TSV chips; and

the top chip is a wire-bond subsequent chip disposed above the TSV third chip.

8. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a through-silicon via (TSV) second chip disposed on the flip chip;

a TSV third chip disposed above the TSV second chip;

a wire-bond fourth chip disposed above the TSV second chip; and

the top chip is a wire-bond subsequent chip disposed above the wire-bond fourth chip.

9. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a wire-bond second chip disposed above the TSV first chip;

a through-silicon via (TSV) third chip disposed above the wire-bond second chip; and

the top chip is a wire-bond subsequent chip disposed above the TSV third chip.

11. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side; and

the top chip is a through-silicon via (TSV) chip disposed on the flip chip.

12. The apparatus of claim 1, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and

at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.

13. A package-on-package stacked-chip apparatus comprising:

a package substrate including a die side and a land side;

a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;

an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and

a top package disposed on the interposer, wherein the top package includes at least one microelectronic device.

14. The apparatus of claim 13, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side; and

the top chip is a through-silicon via (TSV) chip disposed on the flip chip.

15. The apparatus of claim 13, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and

at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.

16. The apparatus of claim 13, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side; and

the top chip is a wire-bond chip disposed on the flip chip.

17. The apparatus of claim 13, wherein the chip stack includes:

the bottom chip is a flip chip mounted on the substrate die side;

a wire-bond second chip disposed on the flip chip; and

the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.

18. A method of assembling a package-on-package stacked-chip apparatus, comprising:

assembling a top package with a ball-grid array to a matching ball-grid array of a 3-dimensional (3D) stacked-chip apparatus, the 3D stacked-chip apparatus including;

a package substrate including a land side and a die side;

a chip stack disposed on the die side, wherein the chip stack has a stack height; and

an interposer including a die side and a top side, wherein the interposer produces an offset height that matches the stack height, and wherein assembling includes mating the top package to the interposer.

19. The method of claim 18, wherein the chip stack is assembled on the package substrate before assembling the interposer to the package substrate.

20. The method of claim 18, wherein the interposer is assembled on the package substrate before assembling the chip stack to the package substrate.

21. The method of claim 18, further including forming a stack encapsulation over the chip stack.

22. The method of claim 18, wherein the chip stack is formed including:

flip-chip mounting a bottom chip on the substrate die side; and

wire-bond mounting a top chip above the flip chip.

23. The method of claim 18, wherein the chip stack is formed including:

flip-chip mounting a bottom chip on the substrate die side;

wire-bond mounting a second chip above the bottom chip; and

wire-bond mounting a top chip above the second chip.

24. The apparatus of claim 18, wherein the chip stack is formed including:

flip chip-mounting a bottom chip on the substrate die side;

through-silicon via (TSV) mounting a second chip on the flip chip; and

wire-bond mounting a subsequent chip as a top chip above the second chip.

25. A computing system, comprising:

a package substrate including a die side and a land side;

a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;

an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and

a top package disposed on the interposer, wherein the top package includes at least one microelectronic device; and

a device housing that contains the top package.

26. The computing system of claim 25, wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.