Multi-chip package and method of providing die-to-die interconnects in same

• US 20100327424A1
• Filed: 06/24/2009
• Published: 12/30/2010
• Est. Priority Date: 06/24/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Au, Hinmeng, Lotz, Stefanie M., Chiu, Chia-Pin, Braunisch, Henning, Swan, Johanna M., Sharan, Sujit, Aleksov, Aleksandar
• Granted Patent: US 8,227,904 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/5381 : Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Claims

1. A multi-chip package comprising:

a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side;

a first die attached to the first side of the substrate and a second die attached to the first side of the substrate; and

a bridge adjacent to the third side of the substrate and attached to the first die and to the second die, wherein no portion of the substrate is underneath the bridge and wherein the bridge creates a connection between the first die and the second die.

2. The multi-chip package of claim 1 wherein:

the bridge comprises silicon.

3. The multi-chip package of claim 1 wherein:

the bridge is attached to the first die and to the second die using flip-chip connections; and

the bridge comprises an active die that constitutes a third die of the multi-chip package.

4. The multi-chip package of claim 3 wherein:

the bridge is attached to the substrate using a wirebond.

5. The multi-chip package of claim 1 wherein:

the third side constitutes a portion of an outside perimeter of the substrate.

6. The multi-chip package of claim 1 wherein:

the third side constitutes a portion of an inside perimeter of the substrate.

7. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:

providing a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side;

attaching a first die to the first side of the substrate such that a portion of the first die extends beyond an edge of the first side of the substrate;

attaching a second die to the first side of the substrate such that a portion of the second die extends beyond the edge of the first side of the substrate;

providing a bridge containing a plurality of electrically or optically conductive features;

positioning the bridge adjacent to the third side of the substrate such that no portion of the substrate is underneath the bridge; and

attaching the bridge to the first die and to the second die, thereby creating a connection between the first die and the second die.

8. The method of claim 7 wherein:

the bridge comprises silicon.

9. The method of claim 8 wherein:

the bridge comprises an active die that constitutes a third die of the multi-chip package; and

the bridge is attached to the first die and to the second die using flip-chip connections.

10. The method of claim 9 further comprising:

attaching the bridge to the substrate using a wirebond.

11. The method of claim 8 wherein:

attaching the bridge comprises using a thermocompression bonding process.

12. The method of claim 8 wherein:

attaching the bridge comprises using a solder reflow process.

13. The method of claim 8 wherein:

providing the substrate comprises forming an aperture through the substrate such that the third side constitutes a portion of an inside perimeter of the substrate.

14. The method of claim 8 wherein:

providing the substrate comprises forming a slot in the substrate such that the third side constitutes a portion of an outside perimeter of the substrate.

15. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:

attaching a first die and a second die to a carrier;

attaching a bridge to the first die and to the second die;

providing a substrate; and

attaching the first die and the second die to the substrate.

16. The method of claim 15 wherein:

the substrate has a cavity therein; and

attaching the first die and the second die to the substrate comprises locating the bridge within the cavity.

17. The method of claim 15 further comprising:

removing the carrier.

18. The method of claim 15 wherein:

the carrier comprises a heat spreader.

19. The method of claim 15 wherein:

attaching the bridge comprises using a thermocompression bonding process.

20. The method of claim 15 wherein:

the bridge comprises silicon.

21. The method of claim 20 wherein:

the bridge comprises an active die that constitutes a third die of the multi-chip package;

the bridge is attached to the first die and to the second die using flip-chip connections; and

the method further comprises attaching the bridge to the substrate using a wirebond.

22. A multi-chip package comprising:

a substrate having a surface;

a first die attached to the surface of the substrate and a second die attached to the surface of the substrate, the first die and the second die forming a die layer of the multi-chip package; and

a bridge attached to the first die and to the second die and located between the die layer and the surface of the substrate.

23. The multi-chip package of claim 22 wherein:

the bridge comprises silicon.

24. The multi-chip package of claim 23 wherein:

the bridge is attached to the first die and to the second die using flip-chip connections;

the bridge comprises an active die that constitutes a third die of the multi-chip package; and

the bridge is attached to the substrate using a wirebond.

25. The multi-chip package of claim 23 wherein:

the first die has a first portion containing a first plurality of interconnect structures and a second portion containing a second plurality of interconnect structures;

the second die has a third portion containing a third plurality of interconnect structures and a fourth portion containing a fourth plurality of interconnect structures;

the first plurality of interconnect structures and the third plurality of interconnect structures have a first pitch;

the second plurality of interconnect structures and the fourth plurality of interconnect structures have a second pitch that is different from the first pitch; and

the first portion and the third portion are attached to the bridge.

26. A multi-chip package comprising:

a substrate containing a cavity having a plurality of pads therein;

a first die attached to the substrate and a second die attached to the substrate;

a bridge having a first side and an opposing second side; and

a plurality of joints at the second side of the bridge,

wherein;

the first die and the second die are attached to the first side of the bridge;

at least a portion of the bridge is located within the cavity such that the plurality of joints are aligned with the plurality of pads; and

the bridge creates a connection between the first die and the second die.

27. The multi-chip package of claim 26 wherein:

the bridge comprises silicon.

28. The multi-chip package of claim 27 wherein:

the bridge is attached to the first die and to the second die using flip-chip connections;

the bridge comprises an active die that constitutes a third die of the multi-chip package; and

the bridge is attached to the substrate using a wirebond.

29. The multi-chip package of claim 27 wherein:

the first die has a first portion containing a first plurality of interconnect structures and a second portion containing a second plurality of interconnect structures;

the second die has a third portion containing a third plurality of interconnect structures and a fourth portion containing a fourth plurality of interconnect structures;

the first plurality of interconnect structures and the third plurality of interconnect structures have a first pitch;

the second plurality of interconnect structures and the fourth plurality of interconnect structures have a second pitch that is different from the first pitch; and

the first portion and the third portion are attached to the bridge.

30. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:

providing a substrate having a plurality of embedded pads;

forming a cavity in the substrate such that the pads are exposed at a floor of the cavity;

providing a bridge having bumps thereon corresponding to the pads;

placing the bridge in the cavity and aligning the bumps and the pads to each other;

providing a first die and a second die; and

attaching the first die and the second die to the bridge and the substrate.

31. The method of claim 30 wherein:

the bridge comprises silicon.

32. The method of claim 31 wherein:

the bridge comprises an active die that constitutes a third die of the multi-chip package;

the bridge is attached to the first die and to the second die using flip-chip connections; and

the method further comprises attaching the bridge to the substrate using a wirebond.

33. The method of claim 31 wherein:

forming the cavity comprises using one of a laser milling and a plasma etching process.

34. A multi-chip package comprising:

a substrate;

a first active die attached to the substrate using a first flip-chip connection; and

a second active die, wherein the second active die is attached to the first active die using a second flip-chip connection and wherein the second active die is also attached to the substrate.

35. The multi-chip package of claim 34 wherein:

the second active die is attached to the substrate using a wirebond.

36. The multi-chip package of claim 35 wherein:

the second active die has a first region and a second region;

the first region is an overlap region located between the substrate and a portion of the first active die; and

the second flip-chip connection is located in the first region of the second active die and the wirebond is attached to the second active die in the second region.

37. The multi-chip package of claim 36 wherein:

the first region of the second active die has a first section and a second section; and

the first section contains a first plurality of flip-chip connections having a first density and the second section contains a second plurality of flip-chip connections having a second density less than the first density.

38. The multi-chip package of claim 37 wherein:

the first region further comprises a third section that contains a third plurality of flip-chip connections having a third density less than the first density; and

the first section is located between the second section and the third section.

39. The multi-chip package of claim 34 wherein:

the substrate contains a cavity; and

the second active die is at least partially located in the cavity.

40. The multi-chip package of claim 34 wherein:

the substrate has a first side, an opposing second side, and a third side that extends from the first side to the second side;

the first active die is attached to the first side of the substrate; and

no portion of the substrate is underneath the second active die.

41. The multi-chip package of claim 34 further comprising:

a third active die attached to the substrate using a third flip-chip connection, wherein the second active die connects the first active die to the third active die.

42. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:

providing a substrate;

attaching a first active die to the substrate using a first flip-chip connection;

attaching a second active die to the first active die using a second flip-chip connection; and

attaching the second active die to the substrate.

43. The method of claim 42 wherein:

the second active die is attached to the substrate using a wirebond.

44. A multi-chip package comprising:

a substrate;

a first active die attached to the substrate using a first flip-chip connection;

a second active die, wherein the second active die is attached to the first active die using a second flip-chip connection and wherein the second active die is also attached to the substrate; and

a third active die attached to the substrate using a third flip-chip connection and attached to the second active die using a fourth flip-chip connection, wherein the second active die connects the first active die to the third active die.

45. The multi-chip package of claim 44 wherein:

the second active die is attached to the substrate using a wirebond.

46. The multi-chip package of claim 45 wherein:

the second active die has a first region, a second region, and a third region;

the first region is a first overlap region located between the substrate and a portion of the first active die;

the third region is a second overlap region located between the substrate and a portion of the third active die;

the second flip-chip connection is located in the first region of the second active die and the wirebond is attached to the second active die in the second region; and

the fourth flip-chip connection is located in the third region of the second active die.

47. The multi-chip package of claim 46 wherein:

the first region of the second die has a first section and a second section;

the third region of the second die has a third section and a fourth section;

the first section contains a first plurality of flip-chip connections having a first density and the second section contains a second plurality of flip-chip connections having a second density less than the first density; and

the third section contains a third plurality of flip-chip connections having a third density and the fourth section contains a fourth plurality of flip-chip connections having a fourth density less than the third density.

48. The multi-chip package of claim 47 wherein:

the second active die comprises electrically or optically conductive traces extending between the first section and the third section; and

the electrically or optically conductive traces connect the first active die to the third active die.

49. The multi-chip package of claim 44 wherein:

the substrate contains a cavity; and

the second active die is at least partially located in the cavity.

50. The multi-chip package of claim 44 wherein:

the substrate has a first side, an opposing second side, and a third side that extends from the first side to the second side;

the first active die and the second active die are attached to the first side of the substrate; and

no portion of the substrate is underneath the second active die.

51. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:

providing a substrate;

attaching a first active die to the substrate using a first flip-chip connection;

attaching a second active die to the substrate using a second flip-chip connection;

attaching a third active die to the first active die using a third flip-chip connection;

attaching the third active die to the second active die using a fourth flip-chip connection; and

attaching the third active die to the substrate.

52. The method of claim 51 wherein:

the third active die is attached to the substrate using a wirebond.