METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS

• US 20100327462A1
• Filed: 09/02/2010
• Published: 12/30/2010
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G.
• Granted Patent: US 8,704,380 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Claims

1. A microfeature assembly, comprising:

a generally rigid, temporary carrier substrate;

a plurality of first known good microelectronic dies releasably attached to the carrier substrate in a desired arrangement, wherein the carrier substrate is patterned with the desired arrangement before the first known good dies are releasably attached;

a plurality of second known good microelectronic dies attached to corresponding first dies in a stacked configuration; and

an encapsulant at least partially encapsulating the first dies and second dies.

2. The assembly of claim 1, further comprising a redistribution layer on the individual second dies.

3. The assembly of claim 1, further comprising a redistribution layer on the individual first dies, wherein the second dies are coupled to the redistribution layers on the first dies.

4. The assembly of claim 1 wherein:

the first dies include an active side adjacent to the carrier substrate, a back side opposite the active side, integrated circuitry, and a plurality of pads at the back side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, and wherein the terminals are electrically coupled to corresponding pads on the first dies.

5. The assembly of claim 1 wherein:

the first dies include an active side adjacent to the carrier substrate, a back side opposite the active side, integrated circuitry, a redistribution layer at the active side, and a plurality of pads at the back side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, and wherein the terminals are electrically coupled to corresponding pads on the first dies.

6. The assembly of claim 1 wherein:

the first dies include an active side, a back side adjacent to the carrier substrate, integrated circuitry, and a plurality of terminals at the active side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of pads electrically coupled to the integrated circuitry, and wherein the pads are electrically coupled to corresponding terminals on the first dies.

7. The assembly of claim 1 wherein:

the first dies include an active side, a back side adjacent to the carrier substrate, integrated circuitry, and a plurality of terminals at the active side electrically coupled to the integrated circuitry, the terminals being arranged on the first dies in a first pattern;

the second dies include integrated circuitry and an array of external contacts electrically coupled to the integrated circuitry, the external contacts being arranged on the second dies in a second pattern different than the first pattern; and

the assembly further comprises a redistribution layer on the individual first dies, the redistribution layers including a plurality of pads arranged in the second pattern.

8. The assembly of claim 1 wherein:

the first dies have a first footprint;

the second dies have a second footprint smaller than the first footprint; and

the assembly further comprises a plurality of third known good microelectronic dies stacked on the individual first dies, the third dies having a third footprint smaller than the first footprint.

9. The assembly of claim 1 wherein:

the first dies include corresponding pairs of devices releasably attached to the carrier substrate, the individual pairs including devices with logic-type circuitry and devices with memory circuitry;

the second dies include integrated circuitry and an image sensor electrically coupled to the integrated circuitry; and

the assembly further comprises optical elements over the individual image sensors.

10. The assembly of claim 1 wherein the carrier substrate includes an attachment feature, and wherein the first dies are releasably attached to the attachment feature.

11. The assembly of claim 1 wherein the temporary carrier substrate has a form factor corresponding to a form factor of a semiconductor wafer.

12. A microfeature assembly, comprising:

a temporary support member;

a plurality of first known good microelectronic dies populating the support member in a desired arrangement, wherein the first dies are releasably attached to the support member, and wherein the support member is patterned with the desired arrangement before the first dies are releasably attached to the support member;

a plurality of second known good microelectronic dies electrically and physically coupled to corresponding first dies in a stacked configuration; and

an encapsulant at least partially encapsulating the first dies and second dies.

13. The assembly of claim 12, further comprising a redistribution layer on the individual second dies.

14. The assembly of claim 12, further comprising a redistribution layer on the individual first dies, wherein the second dies are coupled to the redistribution layers on the first dies.

15. The assembly of claim 12 wherein the temporary support member includes an attachment feature, and wherein the first dies are releasably attached to the attachment feature.

16. The assembly of claim 12 wherein:

the first dies include an active side adjacent to the support member, a back side opposite the active side, integrated circuitry, and a plurality of pads at the back side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, and wherein the terminals are electrically coupled to corresponding pads on the first dies.

17. The assembly of claim 12 wherein:

the first dies include an active side adjacent to the support member, a back side opposite the active side, integrated circuitry, a redistribution layer at the active side, and a plurality of pads at the back side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, and wherein the terminals are electrically coupled to corresponding pads on the first dies.

18. The assembly of claim 12 wherein:

the first dies include an active side, a back side adjacent to the support member, integrated circuitry, and a plurality of terminals at the active side electrically coupled to the integrated circuitry; and

the second dies include integrated circuitry and a plurality of pads electrically coupled to the integrated circuitry, and wherein the pads are electrically coupled to corresponding terminals on the first dies.

19. The assembly of claim 12 wherein:

the first dies include an active side, a back side adjacent to the support member, integrated circuitry, and a plurality of terminals at the active side electrically coupled to the integrated circuitry, the terminals being arranged on the first dies in a first pattern;

the second dies include integrated circuitry and an array of external contacts electrically coupled to the integrated circuitry, the external contacts being arranged on the second dies in a second pattern different than the first pattern; and

the assembly further comprises a redistribution layer on the individual first dies, the redistribution layers including a plurality of pads arranged in the second pattern.

20. The assembly of claim 12 wherein:

the first dies have a first footprint;

the second dies have a second footprint smaller than the first footprint; and

the assembly further comprises a plurality of third known good microelectronic dies stacked on the individual first dies, the third dies having a third footprint smaller than the first footprint.

21. The assembly of claim 12 wherein:

the first dies include corresponding pairs of devices releasably attached to the support member, the individual pairs including devices with logic-type circuitry and devices with memory circuitry;

the second dies include integrated circuitry and an image sensor electrically coupled to the integrated circuitry; and

the assembly further comprises optical elements over the individual image sensors.