Layered chip package

• US 20100327464A1
• Filed: 09/02/2010
• Published: 12/30/2010
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Headway Technologies Incorporated, TDK Corporation
• Original Assignee: Headway Technologies Incorporated, TDK Corporation
• Inventors: Ito, Hiroyuki, Sueki, Satoru, Harada, Tatsuya, Sasaki, Yoshitaka, Okuzawa, Nobuyuki
• Granted Patent: US 8,134,229 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.

Claims

1. A layered chip package comprising:

a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; and

wiring disposed on the first side surface of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions;

the second, third and fourth side surfaces of the semiconductor chip are respectively located at the second, third and fourth side surfaces of the main body;

the first side surface of the semiconductor chip faces toward the first side surface of the main body;

each of the plurality of layer portions further includes;

an insulating portion covering the first side surface of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has an end face located at the first side surface of the main body;

each of the plurality of electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; and

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions.

2. A layered chip package comprising:

a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions;

first wiring disposed on the first side surface of the main body; and

second wiring disposed on the second side surface of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions;

the third and fourth side surfaces of the semiconductor chip are respectively located at the third and fourth side surfaces of the main body;

the first and second side surfaces of the semiconductor chip respectively face toward the first and second side surfaces of the main body;

each of the plurality of layer portions further includes;

an insulating portion covering the first and second side surfaces of the semiconductor chip;

and a plurality of first electrodes and a plurality of second electrodes connected to the semiconductor chip;

the insulating portion has a first end face located at the first side surface of the main body, and a second end face located at the second side surface of the main body;

each of the plurality of first electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion;

each of the plurality of second electrodes has an end face located at the second side surface of the main body and surrounded by the insulating portion;

the first wiring is connected to the end faces of the plurality of first electrodes of the plurality of layer portions; and

the second wiring is connected to the end faces of the plurality of second electrodes of the plurality of layer portions.

3. A layered chip package substructure for use for manufacturing a layered chip package, the layered chip package comprising:

a main body having a top surface, a bottom surface and four side surfaces; and

wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes;

a semiconductor chip having a top surface, a bottom surface and four side surfaces;

an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;

each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions,

the layered chip package substructure corresponding to one of the plurality of layer portions of the layered chip package, including a plurality of its corresponding layer portions, and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions,

the layered chip package substructure comprising a substructure main body fabricated by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the substructure main body including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device, wherein;

the substructure main body has a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer, and has at least one groove that opens at the first surface of the substructure main body and that extends to be adjacent to at least one of the pre-semiconductor-chip portions; and

the at least one groove has a bottom that does not reach the second surface of the substructure main body,

the layered chip package substructure further comprising;

an insulating layer that fills the at least one groove and that will later become part of the insulating portion; and

the plurality of electrodes each having a portion lying on the insulating layer.