VOLTAGE REGULATOR USING DEPLETION MODE PASS DRIVER AND BOOT-STRAPPED, INPUT ISOLATED FLOATING REFERENCE

• US 20100327834A1
• Filed: 03/20/2010
• Published: 12/30/2010
• Est. Priority Date: 06/27/2009
• Status: Active Grant

• Current Assignee: Brian Albert Jr. Lowe
• Original Assignee: Brian Albert Jr. Lowe
• Inventors: Lowe, Brian Albert JR.
• Granted Patent: US 8,294,440 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

Multiple embodiments of a linear voltage regulator are described that use a bipolar output transistor to deliver current and a regulated voltage to a load. The bipolar output transistor assures low output impedance providing isolation from load induced noise. A first depletion mode field effect transistor FET drives the output transistor dependent on a correction signal from an error amplifier. The error amplifier compares a fixed voltage reference to a portion of the output voltage to set a control voltage for the FET gate. Output voltage is set with an offset voltage referenced to circuit ground and can be generated with a single resistor to circuit ground by a current through the resistor which is set from VREF and the regulated output voltage. Output current is limited with a second depletion mode FET that senses the difference in regulator output voltage and voltage at said first FET transistor drain. All circuitry except the output transistor and 2 FET drivers are bootstrap powered from the regulated output voltage to isolate almost all circuit elements from noise present on the input power source.

Claims

1. A voltage regulator circuit comprising:

an input terminal means for receiving power from an input voltage supply;

a common reference terminal means for providing a common voltage;

an offset voltage means for supplying a voltage offset difference between the common reference terminal means and a ground potential terminal means;

an output terminal means for delivering current to a load at a regulated voltage substantially independent of voltage transients on said input voltage supply and substantially independent of current transients on the output terminal means;

a current controlled output transistor having a first electrode connected to said input terminal means, a second electrode connected to said output terminal means and a third electrode means for controlling voltage at said second electrode;

a voltage controlled driver transistor having a first electrode connected to said input terminal means, a second electrode connected to the third electrode means of said current controlled output transistor and a third electrode to control current from the second electrode;

an output voltage sensing means for sensing at least a portion of said regulated voltage between said output terminal means and said offset voltage means;

a reference voltage generating means for generating a reference voltage having an output terminal means and a reference common terminal means; and

an error amplifying means for comparing voltage at said sensing voltage means with output voltage from said reference voltage generating means and for generating a control signal applied to said voltage controlled driver transistor third electrode, said error amplifying means comprising a positive input difference terminal, a negative input difference terminal, a positive power supply terminal, a negative power supply terminal and a difference output terminal.

2. The circuit of claim 1 wherein the voltage controlled driver transistor functions as a current control device with the voltage at the third electrode less than the voltage at the second electrode.

3. The circuit of claim 1 wherein the error amplifying means positive power supply terminal is connected to the output terminal means and the error amplifying means negative power supply terminal is connected to the common reference terminal.

4. The circuit of claim 1 wherein the output voltage sensing means includes a first resistor and a second resistor connected in series, a first end of the first resistor connected to the output terminal means, a second end of the first resistor connected to a first end of the second resistor and also to said error amplifying means negative difference input terminal, and a second end of the second resistor connected to said common reference terminal means.

5. The circuit of claim 1 wherein the offset voltage means is connected between the second resistor second end and said ground potential terminal means.

6. The circuit of claim 1 wherein said reference voltage generating means output terminal means is connected to said error amplifying means positive difference input terminal and a third resistor second end and with reference common terminal means connected to said offset voltage means.

7. The circuit of claim 1 wherein said third resistor first end is connected to the output terminal means, second end connected to the reference voltage generating means output terminal means and the error amplifying means positive difference input terminal, establishing a fixed current through the reference voltage generating means.

8. The circuit of claim 4 wherein a buffer transistor means for conducting the error amplifying means power supply current to said ground potential terminal means is connected between the error amplifier negative power supply terminal and said ground potential terminal means.

9. The circuit of claim 5 wherein said offset voltage means comprises a fourth resistor between the common terminal means and the ground potential terminal, conducting a fixed current established by the sum of currents through said second resistor and said third resistor.

10. The circuit of claim 1 wherein a voltage controlled limit transistor limits current to said output terminal means, the voltage controlled limit transistor having a first electrode connected to said input terminal means, a second electrode connected to the voltage controlled driver transistor first electrode, said voltage controlled driver transistor first electrode no longer connected to said input terminal means, and a third electrode connected to the output terminal means.

11. The circuit of claim 10 wherein the current controlled output transistor has said first terminal connected to a low drop out power supply to provide a voltage less than the voltage supplied by said input terminal means.

12. The circuit of claim 1 wherein the current controlled output transistor has said first terminal connected to a load first terminal, load second terminal connected to a second power supply and said regulated output voltage connected to a fixed resistance first end, with the fixed resistance second end connected to said input voltage supply current return terminal means. Regulator delivers a constant fixed current to said load.

13. The circuit of claim 1 wherein the offset reference terminal is connected to an AC plus DC voltage source means for modulating the voltage at the output terminal means.

14. The circuit of claim 1 wherein complementary polarity devices deliver a complimentary polarity voltage at the output terminal means.