BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN
First Claim
1. A bridge device for controlling discrete memory devices in response to global command, comprising:
- a first clock domain having first logic circuits and first control circuits operating in synchronization with a memory clock for issuing local commands to the discrete memory devices;
a frequency controller for generating the memory clock as one of at least two dynamically selectable clock divide ratios of a system clock provided to the bridge device; and
a second clock domain having second logic circuit and second control circuits operating in synchronization with the system clock for converting the global command received synchronously with the system clock into the local command synchronized with the memory clock.
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Accused Products
Abstract
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.
25 Citations
28 Claims
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1. A bridge device for controlling discrete memory devices in response to global command, comprising:
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a first clock domain having first logic circuits and first control circuits operating in synchronization with a memory clock for issuing local commands to the discrete memory devices; a frequency controller for generating the memory clock as one of at least two dynamically selectable clock divide ratios of a system clock provided to the bridge device; and a second clock domain having second logic circuit and second control circuits operating in synchronization with the system clock for converting the global command received synchronously with the system clock into the local command synchronized with the memory clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification