IMAGE DISPLAY APPARATUS AND CONTROL METHOD THEREFOR
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Abstract
An image display apparatus comprises a pixel having a drive transistor and a pixel display element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of the drive transistor, and a selection transistor connected between a signal line and the gate electrode of the drive transistor. When the selection transistor is turned on, gradation pixel data is written in the holding capacitor from the signal line. The charge of gradation pixel data written in the holding capacitor is discharged for a certain period through the drive transistor, thereafter the charge of the gradation pixel data stored in the holding capacitor is held by floating the gate electrode of the drive transistor.
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Citations
52 Claims
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1-42. -42. (canceled)
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43. An image display apparatus comprising:
- a pixel having a drive transistor and a pixel display element which are electrically connected in series between a first power line and a second power line, a holding capacitor electrically connected to a gate electrode of said drive transistor, and a selection transistor electrically connected between a signal line and the gate electrode of said drive transistor; and
a controller for turning on said selection transistor thereby to write gradation pixel data in said holding capacitor from said signal line, discharging charges of the gradation pixel data written in said holding capacitor through said drive transistor for a predetermined time less than a frame time, and thereafter floating the gate electrode of said drive transistor thereby to hold the charges of the gradation pixel data stored in said holding capacitor. - View Dependent Claims (44, 45, 46)
- a pixel having a drive transistor and a pixel display element which are electrically connected in series between a first power line and a second power line, a holding capacitor electrically connected to a gate electrode of said drive transistor, and a selection transistor electrically connected between a signal line and the gate electrode of said drive transistor; and
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47. A control method for an image display apparatus including a pixel having a drive transistor and a pixel display element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of said drive transistor, and a selection transistor connected between a signal line and the gate electrode of said drive transistor, comprising:
- a pixel data writing step of turning on said selection transistor thereby to write gradation pixel data in said holding capacitor from said signal line;
a discharging step of discharging charges of the gradation pixel data written in said holding capacitor through said drive transistor for a predetermined time less than a frame time; and
after said discharging step, a pixel data holding step of floating the gate electrode of said drive transistor thereby to hold the charges of the gradation pixel data stored in said holding capacitor. - View Dependent Claims (48, 49, 50)
- a pixel data writing step of turning on said selection transistor thereby to write gradation pixel data in said holding capacitor from said signal line;
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51. An image display apparatus comprising:
a pixel having a drive transistor and a pixel display element which are electrically connected in a series between a first power line and a second power line, a holding capacitor electrically connected between a gate electrode of said drive transistor and a junction node, and a selection transistor electrically connected between a signal line and the gate electrode of said drive transistor, said junction node being of between said pixel display element and a source electrode of said drive transistor.
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52. An image display apparatus comprising:
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a pixel having a drive transistor and a pixel display element which are electrically connected in a series between a first power line and a second power line, a holding capacitor electrically connected between a gate electrode of said drive transistor and a source electrode of said drive transistor, a selection transistor electrically connected between a signal line and the gate electrode of said drive transistor; and a controller for discharging charges written in said holding capacitor for a predetermined time less than a frame time, and thereafter floating the gate electrode of said drive transistor thereby to hold the charges of the gradation pixel data stored in said holding capacitor.
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Specification