Register Allocation for Message Sends in Graphics Processing Pipelines

• US 20100328334A1
• Filed: 06/26/2009
• Published: 12/30/2010
• Est. Priority Date: 06/26/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chen, Wei-Yu, Lueh, Guei-Yuan
• Granted Patent: US 8,237,726 B2
• Time in Patent Office: Days
• US Class Current: 345/589
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.

Claims

1. A method comprising:

allocating registers for message sends in graphics processing using biased graph coloring.

2. The method of claim 1 including using biased graph coloring for send messages from shaders in a graphics pipeline.

3. The method of claim 1 including coalescing message sources with actual sources of a send instruction.

4. The method of claim 3 including favoring sources to be assigned to the same physical register as a corresponding message source.

5. The method of claim 1 including assigning preferred colors to live ranges without checking for interferences.

6. The method of claim 5 including resolving conflicts during a biased graph coloring operation.

7. The method of claim 1 including using heuristics to pick one of a plurality of physical registers to be a preferred color.

8. The method of claim 7 including using heuristics to pick the physical register with the most number of message sends.

9. The method of claim 1 including assigning colors to nodes with a preferred color first.

10. The method of claim 1 including avoiding the use of physical registers assigned to send sources for live ranges without a preferred color.

11. The method of claim 1 including avoiding assigning to a live range the preferred color of its neighbors.

18. The apparatus of claim 11, said shader to use heuristics to pick one of a plurality of physical registers to be a preferred color.

19. The apparatus of claim 18, said shader to use heuristics to pick the physical register with the most number of message sends.

12. An apparatus comprising:

a graphics pipeline including a plurality of shaders;

a plurality of registers for message sends in said graphics pipeline; and

a shader to allocate registers for message sends using biased graph coloring.

13. The apparatus of claim 12, said shader to use biased graph coloring for said send messages.

14. The apparatus of claim 12, said shader to coalesce message sources with actual sources of a send instruction.

15. The apparatus of claim 14, said shader to favor sources to be assigned to the same physical register as a corresponding message source.

16. The apparatus of claim 12, said shader to assign preferred colors to live ranges without checking for interferences.

17. The apparatus of claim 16, said shader to resolve conflicts during a biased graph coloring operation.

20. The apparatus of claim 12, said shader to assign colors to nodes with the preferred color first.