SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

• US 20100329005A1
• Filed: 06/30/2010
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YANG, Chang Won
• Granted Patent: US 8,503,232 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines.

Claims

1. A programming method comprising:

classifying memory cells to be programmed into first, second and third levels;

applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and

supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines.

2. The programming method according to claim 1, wherein the first level is higher than a threshold voltage of an erased voltage, the second level is higher than the first voltage, and the third level is higher than the second voltage.

3. The programming method according to claim 1, wherein classifying the memory cells to be programmed into the first, second and third levels comprises:

inputting program data into page buffers coupled with the bit lines and classifying the levels to program the memory cells in accordance with the input data.

4. The programming method according to claim 1, wherein a program pass voltage is applied to unselected word lines but is not applied to the selected word line.

5. The programming method according to claim 1, wherein the program voltage is supplied at the same level even if another word line is selected.

6. A programming method comprising:

classifying memory cells, which are to be programmed, in accordance with a program level;

providing a voltage, which is inversely proportional to the program level, to bit lines of the memory cells that are to be programmed; and

supplying a program voltage into the memory cells, which are to be programmed, while providing the voltage to the bit lines.

7. The programming method according to claim 6, wherein the memory cells to be programmed are classified by inputting program data into page buffers each coupled with the bit lines, wherein the voltage inversely proportional to the program level is provided to the bit lines in accordance with the program data.

8. A semiconductor memory device comprising:

a plurality of strings each including a plurality of memory cells; and

page buffers coupled with the strings respectively through bit lines and configured to provide bit line voltages of various levels into the bit lines in accordance with program levels of memory cells that are to be programmed.

9. The semiconductor memory device according to claim 8, wherein the page buffer comprises:

a bit line selector configured to couple a sensing node with a selected one of the bit lines;

a precharge circuit configured to transfer a precharge voltage to the sensing node;

a voltage controller configured to provide a voltage of various levels to the sensing node; and

a latch circuit coupled with the sensing node and configured to receive data that is to be programmed.

10. The semiconductor memory device according to claim 9, wherein the voltage controller comprises:

two switches serially coupled between a terminal of a power source voltage and the sensing node; and

a third switch coupled between a gate line of one of the two switches and the sensing node.

11. The semiconductor memory device according to claim 10, wherein the third switch operates in compliance with a first control signal that is generated from a voltage generator.

12. The semiconductor memory device according to claim 11, wherein a voltage applied to the sensing node is dependent on a voltage level of the first control signal.

13. The semiconductor memory device according to claim 10, wherein the switches are made of NMOS transistors.

14. A programming method comprising:

controlling voltages applied to a plurality of bit lines of a memory cell array according to program levels of memory cells; and

applying a program voltage to a selected word line to arrive threshold voltages of the memory cells at target voltage levels.

15. The programming method according to claim 14, wherein the voltages applied to the plurality of bit lines are increased when the program levels are low, and the voltages applied to the plurality of bit lines are decreased when the program levels are high.

16. A method of programming a memory device comprising:

providing, by page buffers coupled with strings of memory cells respectively through bit lines, bit line voltages of various levels into the bit lines in accordance with program levels of memory cells within the strings that are to be programmed.