MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE
First Claim
1. A memory system on a single chip, comprising:
- a NAND flash memory having a status register and a plurality of NAND cells, said plurality of NAND cells having a plurality of bit lines, a plurality of source lines in parallel with said bit lines, and a plurality of word lines perpendicular to said bit lines and said source lines;
a NOR flash memory having a status register and a plurality of NOR cells, each of said NOR cells being formed by a symmetrical 2-NAND cell string and having a drain connected to a bit line, a source connected to a source line in parallel with said bit line and two floating gates connected to two word lines perpendicular to said bit line and said source line;
an address bus shared by said NAND and NOR flash memories, anda data bus shared by said NAND and NOR flash memories;
wherein both said address bus and said data bus are bi-directional for receiving external inputs to said memory system and transmitting outputs from said memory system, and said NAND and NOR flash memories are manufactured by a unified NAND manufacturing process and same NAND cells.
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Abstract
A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.
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Citations
73 Claims
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1. A memory system on a single chip, comprising:
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a NAND flash memory having a status register and a plurality of NAND cells, said plurality of NAND cells having a plurality of bit lines, a plurality of source lines in parallel with said bit lines, and a plurality of word lines perpendicular to said bit lines and said source lines; a NOR flash memory having a status register and a plurality of NOR cells, each of said NOR cells being formed by a symmetrical 2-NAND cell string and having a drain connected to a bit line, a source connected to a source line in parallel with said bit line and two floating gates connected to two word lines perpendicular to said bit line and said source line; an address bus shared by said NAND and NOR flash memories, and a data bus shared by said NAND and NOR flash memories; wherein both said address bus and said data bus are bi-directional for receiving external inputs to said memory system and transmitting outputs from said memory system, and said NAND and NOR flash memories are manufactured by a unified NAND manufacturing process and same NAND cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73)
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Specification