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MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE

  • US 20100329011A1
  • Filed: 02/05/2010
  • Published: 12/30/2010
  • Est. Priority Date: 06/30/2009
  • Status: Active Grant
First Claim
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1. A memory system on a single chip, comprising:

  • a NAND flash memory having a status register and a plurality of NAND cells, said plurality of NAND cells having a plurality of bit lines, a plurality of source lines in parallel with said bit lines, and a plurality of word lines perpendicular to said bit lines and said source lines;

    a NOR flash memory having a status register and a plurality of NOR cells, each of said NOR cells being formed by a symmetrical 2-NAND cell string and having a drain connected to a bit line, a source connected to a source line in parallel with said bit line and two floating gates connected to two word lines perpendicular to said bit line and said source line;

    an address bus shared by said NAND and NOR flash memories, anda data bus shared by said NAND and NOR flash memories;

    wherein both said address bus and said data bus are bi-directional for receiving external inputs to said memory system and transmitting outputs from said memory system, and said NAND and NOR flash memories are manufactured by a unified NAND manufacturing process and same NAND cells.

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