SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL AND DATA WRITING METHOD THEREOF
First Claim
1. A semiconductor memory device comprising:
- a plurality of nonvolatile memory cells in which pieces of data are stored as thresholds having different levels;
a plurality of bit lines which are connected to the nonvolatile memory cells;
a first control circuit which supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changing a supply state of the write control voltage to further write the data when the selected memory cell reaches a first write state by the write, the first control circuit further changing the supply state of the write control voltage to prohibit the write when the selected memory cell reaches a second write state by the write; and
a second control circuit which controls a rising of the write control voltage when the first control circuit starts the writing to make the selected memory cell the second write state.
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Accused Products
Abstract
A semiconductor memory device includes memory cells, bit lines, and first and second control circuits. The first control circuit supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changes a supply state of the write control voltage to further write the data when the selected memory cell reaches a first write state by the write, the first control circuit further changes the supply state of the write control voltage to prohibit the write when the selected memory cell reaches a second write state by the write. The second control circuit controls a rising of the write control voltage when the first control circuit starts the writing to make the selected memory cell the second write state.
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Citations
18 Claims
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1. A semiconductor memory device comprising:
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a plurality of nonvolatile memory cells in which pieces of data are stored as thresholds having different levels; a plurality of bit lines which are connected to the nonvolatile memory cells; a first control circuit which supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changing a supply state of the write control voltage to further write the data when the selected memory cell reaches a first write state by the write, the first control circuit further changing the supply state of the write control voltage to prohibit the write when the selected memory cell reaches a second write state by the write; and a second control circuit which controls a rising of the write control voltage when the first control circuit starts the writing to make the selected memory cell the second write state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 13)
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11. A method for writing data of a semiconductor memory device, comprising:
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supplying a write voltage and a write control voltage to a memory cell to perform first write of data to the memory cell; changing a supply state of the write control voltage to perform second write when the memory cell reaches a first write state by the first write; and changing further the supply state of the write control voltage to prohibit the write when the memory cell reaches a second write state by the second write, wherein a rising speed of the write control voltage is slowed. - View Dependent Claims (12, 14)
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15. A method for writing data of a semiconductor memory device, comprising:
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supplying a write voltage and a write control voltage to a memory cell to perform first write of data to the memory cell; changing a supply state of the write control voltage to perform second write when the memory cell reaches a first write state by the first write; and changing further the supply state of the write control voltage to prohibit the write when the memory cell reaches a second write state by the second write, wherein a rising timing of the write control voltage is delayed in the second write. - View Dependent Claims (16, 17, 18)
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Specification